8.2. FIFO IP Core Parameters for Intel® MAX® 10 Devices
| Parameter | HDL Parameter | Description |
|---|---|---|
| How wide should the FIFO be? | lpm_width | Specifies the width of the data and q ports for the FIFO IP core in SCFIFO mode and DCFIFO mode. |
| Usedw[] | lpm_widthu | Specifies the width of the usedw port for the FIFO IP core in SCFIFO mode, or the width of the rdusedw and wrusedw ports for the FIFO IP core in DCFIFO mode. |
| How deep should the FIFO be? | lpm_numwords | Specifies the depths of the FIFO you require. The value must be at least 4. The value assigned must comply with the 2LPM_WIDTHU equation. |
| Which kind of read access do you want with the rdreq signal? | lpm_showahead | Specifies whether the FIFO is in normal synchronous FIFO mode or show-ahead mode synchronous FIFO mode. For normal synchronous FIFO mode, the FIFO IP core treats the rdreq port as a normal read request that only performs read operation when the port is asserted. For show-ahead mode synchronous FIFO mode, the FIFO IP core treats the rdreq port as a read-acknowledge that automatically outputs the first word of valid data in the FIFO IP core (when the empty or rdempty port is low) without asserting the rdreq signal. Asserting the rdreq signal causes the FIFO IP core to output the next data word, if available. If you turn on this parameter, you may reduce performance. |
| Do you want a common clock for reading and writing the FIFO? | lpm_type | Identifies the library of parameterized modules (LPM) entity name. The values are SCFIFO and DCFIFO. |
| Disable overflow checking. Writing to a full FIFO will corrupt contents | overflow_checking | Specifies whether or not to enable the protection circuitry for overflow checking that disables the wrreq port when the FIFO IP core is full. This parameter is enabled by default. |
| Disable underflow checking. Reading from an empty FIFO will corrupt contents. | underflow_checking | Specifies whether or not to enable the protection circuitry for underflow checking that disables the rdreq port when the FIFO IP core is empty. This parameter is enabled by default. Note that reading from an empty SCFIFO mode gives unpredictable results. |
| Add an extra MSB to usedw 1 | add_usedw_msb_bit | Increases the width of the rdusedw and wrusedw ports by one bit. By increasing the width, it prevents the FIFO IP core from rolling over to zero when it is full. This parameter is disabled by default. |
| How many sync stages? 1 | rdsync_delaypipe | Specifies the number of synchronization stages in the cross clock domain. The value of the rdsync_delaypipe parameter relates the synchronization stages from the write control logic to the read control logic; the wrsync_delaypipe parameter relates the synchronization stages from the read control logic to the write control logic. Use these parameters to set the number of synchronization stages if the clocks are not synchronized, and set the clocks_are_synchronized parameter to FALSE. The actual synchronization stage implemented relates variously to the parameter value assigned and depends on the target device. |
| How many sync stages? 1 | wrsync_delaypipe | Specifies the number of synchronization stages in the cross clock domain. The value of the rdsync_delaypipe parameter relates the synchronization stages from the write control logic to the read control logic; the wrsync_delaypipe parameter relates the synchronization stages from the read control logic to the write control logic. Use these parameters to set the number of synchronization stages if the clocks are not synchronized, and set the clocks_are_synchronized parameter to FALSE. The actual synchronization stage implemented relates variously to the parameter value assigned and depends on the target device. |
| Implement FIFO storage with logic cells only, even if the device contains memory blocks. | use_eab | Specifies whether or not the FIFO IP core is constructed using RAM blocks. This parameter is disabled by default. If you turn off this parameter, the FIFO IP core is implemented in logic elements, regardless of the memory block type assigned to the What should the memory block type be parameter. |
| Add circuit to synchronize ‘aclr’ input with ‘wrclk’ 1 | write_aclr_synch | Specifies whether or not to add a circuit that causes the aclr port to be internally synchronized by the wrclk clock. Adding the circuit prevents the race condition between the wrreq and aclr ports that could corrupt the FIFO IP core. This parameter is disabled by default. |
| Add circuit to synchronize ‘aclr’ input with ‘rdclk’ | read_aclr_synch | Specifies whether or not to add a circuit that causes the aclr port to be internally synchronized by the rdclk clock. Adding the circuit prevents the race condition between the rdreq and aclr ports that could corrupt the FIFO IP core. This parameter is disabled by default. |
| Which type of optimization do you want? 1 | clocks_are_synchronized | Specifies whether or not the write and read clocks are synchronized, which in turn determines the number of internal synchronization stages added for stable operation of the FIFO. The values are TRUE and FALSE. If omitted, the default value is FALSE. You must only set the parameter to TRUE if the write clock and the read clock are always synchronized and they are multiples of each other. Otherwise, set this to FALSE to avoid metastability problems. If the clocks are not synchronized, set the parameter to FALSE, and use the rdsync_delaypipe and wrsync_delaypipe parameters to determine the number of synchronization stages required. |
| What should the memory block type be | ram_block_type | Specifies the target device’s memory block to be used. To get the proper implementation based on the RAM configuration that you set, allow the Intel® Quartus® Prime software to automatically choose the memory type by ignoring this parameter and turn on the Implement FIFO storage with logic cells only, even if the device contains memory blocks. parameter. This gives the Compiler the flexibility to place the memory function in any available memory resource based on the FIFO depth required. |
| Would you like to register the output to maximize the performance but use more area? 2 | add_ram_output_register | Specifies whether to register the q output. The values are Yes (best speed) and No (smallest area). The default value is No (smallest area). |
| Becomes true when usedw[] is greater than or equal to: 2 | almost_full_value | Sets the threshold value for the almost_full port. When the number of words stored in the FIFO IP core is greater than or equal to this value, the almost_full port is asserted. |
| Almost full 2 | ||
| Almost empty 2 | almost_empty_value | Sets the threshold value for the almost_empty port. When the number of words stored in the FIFO IP core is less than this value, the almost_empty port is asserted. |
| Becomes true when usedw[] is less than: 2 | ||
| Currently selected device family | intended_device_family | Specifies the intended device that matches the device set in your Intel® Quartus® Prime project. Use this parameter only for functional simulation. |
1 Applicable in DCFIFO mode only.
2 Applicable in SCFIFO mode only.