Intel® MAX™ 10 Embedded Memory User Guide

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ID 683431
Date 5/05/2023
Public
Document Table of Contents
Document Table of Contents x
1. Intel® MAX® 10 Embedded Memory Overview 2. Intel® MAX® 10 Embedded Memory Architecture and Features 3. Intel® MAX® 10 Embedded Memory Design Consideration 4. RAM: 1-Port IP Core References 5. RAM: 2-PORT IP Core References 6. ROM: 1-PORT IP Core References 7. ROM: 2-PORT IP Core References 8. FIFO IP Core References 9. Shift Register (RAM-based) IP Core References 10. ALTMEMMULT IP Core References 11. Document Revision History for the Intel® MAX® 10 Embedded Memory User Guide
2. Intel® MAX® 10 Embedded Memory Architecture and Features x
2.1. Intel® MAX® 10 Embedded Memory General Features 2.2. Intel® MAX® 10 Embedded Memory Operation Modes 2.3. Intel® MAX® 10 Embedded Memory Clock Modes 2.4. Intel® MAX® 10 Embedded Memory Configurations
2.1. Intel® MAX® 10 Embedded Memory General Features x
2.1.1. Control Signals 2.1.2. Parity Bit 2.1.3. Read Enable 2.1.4. Read-During-Write 2.1.5. Byte Enable 2.1.6. Packed Mode Support 2.1.7. Address Clock Enable Support 2.1.8. Asynchronous Clear
2.1.5. Byte Enable x
2.1.5.1. Byte Enable Controls 2.1.5.2. Data Byte Output 2.1.5.3. RAM Blocks Operations
2.1.7. Address Clock Enable Support x
2.1.7.1. Address Clock Enable During Read Cycle Waveform 2.1.7.2. Address Clock Enable During Write Cycle Waveform
2.1.8. Asynchronous Clear x
2.1.8.1. Resetting Registers in M9K Blocks
2.2. Intel® MAX® 10 Embedded Memory Operation Modes x
2.2.1. Supported Memory Operation Modes
2.3. Intel® MAX® 10 Embedded Memory Clock Modes x
2.3.1. Asynchronous Clear in Clock Modes 2.3.2. Output Read Data in Simultaneous Read and Write 2.3.3. Independent Clock Enables in Clock Modes
2.4. Intel® MAX® 10 Embedded Memory Configurations x
2.4.1. Port Width Configurations 2.4.2. Memory Configurations for Single-Port Modes 2.4.3. Memory Configurations for Dual-Port Modes 2.4.4. Maximum Block Depth Configuration
3. Intel® MAX® 10 Embedded Memory Design Consideration x
3.1. Implement External Conflict Resolution 3.2. Customize Read-During-Write Behavior 3.3. Consider Power-Up State and Memory Initialization 3.4. Control Clocking to Reduce Power Consumption 3.5. Selecting Read-During-Write Output Choices
3.2. Customize Read-During-Write Behavior x
3.2.1. Same-Port Read-During-Write Mode 3.2.2. Mixed-Port Read-During-Write Mode
3.2.2. Mixed-Port Read-During-Write Mode x
3.2.2.1. Mixed-Port Read-During-Write Operation with Dual Clocks
4. RAM: 1-Port IP Core References x
4.1. RAM: 1-Port IP Core Signals For Intel® MAX® 10 Devices 4.2. RAM: 1-Port IP Core Parameters For Intel® MAX® 10 Devices
5. RAM: 2-PORT IP Core References x
5.1. RAM: 2-Ports IP Core Signals (Simple Dual-Port RAM) For Intel® MAX® 10 Devices 5.2. RAM: 2-Port IP Core Signals (True Dual-Port RAM) for Intel® MAX® 10 Devices 5.3. RAM: 2-Port IP Core Parameters for Intel® MAX® 10 Devices
6. ROM: 1-PORT IP Core References x
6.1. ROM: 1-PORT IP Core Signals For Intel® MAX® 10 Devices 6.2. ROM: 1-PORT IP Core Parameters for Intel® MAX® 10 Devices
7. ROM: 2-PORT IP Core References x
7.1. ROM: 2-PORT IP Core Signals for Intel® MAX® 10 Devices 7.2. ROM: 2-Port IP Core Parameters For Intel® MAX® 10 Devices
8. FIFO IP Core References x
8.1. FIFO IP Core Signals for Intel® MAX® 10 Devices 8.2. FIFO IP Core Parameters for Intel® MAX® 10 Devices 8.3. FIFO Functional Timing Requirements 8.4. SCFIFO ALMOST_EMPTY Functional Timing
9. Shift Register (RAM-based) IP Core References x
9.1. Shift Register (RAM-based) IP Core Signals for Intel® MAX® 10 Devices 9.2. Shift Register (RAM-based) IP Core Parameters for Intel® MAX® 10 Devices
10. ALTMEMMULT IP Core References x
10.1. ALTMEMMULT IP Core Signals for Intel® MAX® 10 Devices 10.2. ALTMEMMULT IP Core Parameters for Intel® MAX® 10 Devices
1. Intel® MAX® 10 Embedded Memory Overview
2. Intel® MAX® 10 Embedded Memory Architecture and Features
3. Intel® MAX® 10 Embedded Memory Design Consideration
4. RAM: 1-Port IP Core References
5. RAM: 2-PORT IP Core References
6. ROM: 1-PORT IP Core References
7. ROM: 2-PORT IP Core References
8. FIFO IP Core References
9. Shift Register (RAM-based) IP Core References
10. ALTMEMMULT IP Core References
11. Document Revision History for the Intel® MAX® 10 Embedded Memory User Guide

8. FIFO IP Core References

The FIFO IP core implements the FIFO mode, enabling you to use the memory blocks as FIFO buffers.

  • Use the FIFO IP core in single clock FIFO (SCFIFO) and dual clock FIFO (DCFIFO) modes to implement single- and dual-clock FIFO buffers in your design.
  • Dual clock FIFO buffers are useful when transferring data from one clock domain to another clock domain.
  • The M9K memory blocks do not support simultaneous read and write from an empty FIFO buffer.
Figure 24.  FIFO IP Core: SCFIFO Mode Signals
Figure 25. FIFO IP Core: DCFIFO Mode Signals

Section Content
FIFO IP Core Signals for Intel MAX 10 Devices
FIFO IP Core Parameters for Intel MAX 10 Devices
FIFO Functional Timing Requirements
SCFIFO ALMOST_EMPTY Functional Timing

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