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1. Intel® Stratix® 10 Embedded Memory Overview
2. Intel® Stratix® 10 Embedded Memory Architecture and Features
3. Intel® Stratix® 10 Embedded Memory Design Considerations
4. Intel® Stratix® 10 Embedded Memory IP References
5. Intel Stratix 10 Embedded Memory Design Example
6. Intel® Stratix® 10 Embedded Memory User Guide Archives
7. Document Revision History for the Intel® Stratix® 10 Embedded Memory User Guide
2.1. Byte Enable in Intel® Stratix® 10 Embedded Memory Blocks
2.2. Address Clock Enable Support
2.3. Asynchronous Clear and Synchronous Clear
2.4. Memory Blocks Error Correction Code Support
2.5. Force-to-Zero
2.6. Coherent Read Memory
2.7. Freeze Logic
2.8. True Dual Port Dual Clock Emulator
2.9. 'X' Propagation Support in Simulation
2.10. Intel® Stratix® 10 Supported Embedded Memory IPs
2.11. Intel® Stratix® 10 Embedded Memory Clocking Modes
2.12. Intel® Stratix® 10 Embedded Memory Configurations
2.13. Initial Value of Read and Write Address Registers
3.1. Consider the Memory Block Selection
3.2. Consider the Concurrent Read Behavior
3.3. Customize Read-During-Write Behavior
3.4. Consider Power-Up State and Memory Initialization
3.5. Reduce Power Consumption
3.6. Avoid Providing Non-Deterministic Input
3.7. Avoid Changing Clock Signals and Other Control Signals Simultaneously
3.8. Including the Reset Release Intel® FPGA IP in Your Design
4.1.1. Release Information for RAM and ROM Intel® FPGA IPs
4.1.2. RAM: 1-PORT Intel® FPGA IP Parameters
4.1.3. RAM: 2-PORT Intel® FPGA IP Parameters
4.1.4. RAM: 4-PORT Intel® FPGA IP Parameters
4.1.5. ROM: 1-PORT Intel® FPGA IP Parameters
4.1.6. ROM: 2-PORT Intel® FPGA IP Parameters
4.1.7. RAM and ROM Interface Signals
4.1.8. Changing Parameter Settings Manually
4.3.1. Release Information for FIFO Intel® FPGA IP
4.3.2. Configuration Methods
4.3.3. Specifications
4.3.4. FIFO Functional Timing Requirements
4.3.5. SCFIFO ALMOST_EMPTY Functional Timing
4.3.6. FIFO Output Status Flag and Latency
4.3.7. FIFO Metastability Protection and Related Options
4.3.8. FIFO Synchronous Clear and Asynchronous Clear Effect
4.3.9. SCFIFO and DCFIFO Show-Ahead Mode
4.3.10. Different Input and Output Width
4.3.11. DCFIFO Timing Constraint Setting
4.3.12. Coding Example for Manual Instantiation
4.3.13. Design Example
4.3.14. Gray-Code Counter Transfer at the Clock Domain Crossing
4.3.15. Guidelines for Embedded Memory ECC Feature
4.3.16. FIFO Intel® FPGA IP Parameters
4.3.17. Reset Scheme
4.4.1. Release Information for FIFO2 Intel® FPGA IP
4.4.2. Configuration Methods
4.4.3. Fmax Target Measuring Methodology
4.4.4. Performance Considerations
4.4.5. FIFO2 Intel® FPGA IP Features
4.4.6. FIFO2 Intel® FPGA IP Parameters
4.4.7. FIFO2 Intel® FPGA IP Interface Signals
4.4.8. Reset and Clock Schemes
4.5.1. Release Information for Shift Register (RAM-based) Intel® FPGA IP
4.5.2. Shift Register (RAM-based) Intel® FPGA IP Features
4.5.3. Shift Register (RAM-based) Intel® FPGA IP General Description
4.5.4. Shift Register (RAM-based) Intel® FPGA IP Parameter Settings
4.5.5. Shift Register Ports and Parameters Setting
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4.1.6. ROM: 2-PORT Intel® FPGA IP Parameters
This table lists the parameters for the ROM: 2-PORT Intel® FPGA IP.
Parameter | Legal Values | Description | |
---|---|---|---|
Parameter Settings: Widths/Blk Type | |||
How do you want to specify the memory size? |
|
Determines whether to specify the memory size in words or bits. | |
How many words of memory? | 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768, or 65536 | Specifies the number of words. | |
Use different data widths on different ports | On/Off | Specifies whether to use different data widths on different ports. | |
How wide should the ‘q_a’ output bus be? | — | Specifies the width of the ‘q_a’ and ‘q_b’ output ports. | |
How wide should the ‘q_b’ output bus be? | |||
RAM block type | Auto, M20K | Specifies the memory block type. The types of memory block that are available for selection depends on your target device | |
Set the maximum block depth to: |
|
Specifies the maximum block depth in words. This option is enabled only when you choose Auto as the memory block type. | |
Parameter Settings: Clks/Rd | |||
What clocking method would you like to use? |
|
Specifies the clocking method to use.
|
|
Create a ‘rden_a’ and ‘rden_b’ read enable signals | On/Off | Specifies whether to create read enable signals. | |
Parameter Settings: Regs/Clkens/Aclrs | |||
Which ports should be registered? Read output ports |
On/Off | Specifies whether to register the read output ports. | |
More Options | Registered Q Output Ports
|
On/Off | Turn on if you want the registered ‘q_a’ and ‘q_b’ ports to be affected by the asynchronous clear signal.
|
Use clock enable for port A input registers | On/Off | Specifies whether to use clock enable for port A input registers. | |
Use clock enable for port A output registers | On/Off | Specifies whether to use clock enable for port A output registers. | |
Use clock enable for port B input registers | On/Off | Specifies whether to use clock enable for port B input registers. | |
Use clock enable for port B output registers | On/Off | Specifies whether to use clock enable for port B output registers. | |
Aclr Options
|
On/Off | Specifies whether the registered ports should be cleared by the asynchronous clear port. | |
Sclr Options
|
On/Off | Specifies whether the registered ports should be cleared by the synchronous clear port. | |
Parameter Settings: Mem Init | |||
Do you want to specify the initial content of the memory? |
|
Specifies the initial content of the memory. In ROM mode, you must specify a memory initialization file (.mif) or a hexadecimal (Intel-format) file (.hex). The Yes, use this file for the memory content data option is turned on by default. |
|
The initial content file should conform to which port’s dimensions? |
|
Specifies whether the initial content file conforms to port A or port B. | |
Parameter Settings: Performance Optimization | |||
Enable Force-to-Zero | On/Off | Specifies whether to set the output to zero when you deassert the read enable signal. Enabling this feature helps improve the glue logic performance when the selected memory depth is larger than a single memory block. |