Visible to Intel only — GUID: eis1414481001345
Ixiasoft
Visible to Intel only — GUID: eis1414481001345
Ixiasoft
4.3.8.1. Recovery and Removal Timing Violation Warnings when Compiling a DCFIFO
You may safely ignore warnings that represent transfers from aclr to the read side clock domain. To ensure that the design meets timing, enable the ACLR synchronizer for both read and write domains.
To enable the ACLR synchronizer for both read and write domains, on the DCFIFO 2 tab of the FIFO Intel® FPGA IP core, turn on Asynchronous clear, Add circuit to synchronize ‘aclr’ input with ‘wrclk’, and Add circuit to synchronize ‘aclr’ input with ‘rdclk’.
When the Add circuit to synchronize ‘aclr’ input with ‘wrclk’ and Add circuit to synchronize ‘aclr’ input with ‘rdclk’ options are enabled, you can apply the following false path assignment on the reset path:
- set_false_path -to *dcfifo:dcfifo_component|dcfifo_*:auto_generated|dffpipe_*:wraclr|dffe*a[0]
- set_false_path -to *dcfifo:dcfifo_component|dcfifo_*:auto_generated|dffpipe_*:rdaclr|dffe*a[0]
While the metastability issue is resolved by the circuit, the system design still requires a certain maximum delay even though it is asynchronous.