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1. Intel® Stratix® 10 Embedded Memory Overview
2. Intel® Stratix® 10 Embedded Memory Architecture and Features
3. Intel® Stratix® 10 Embedded Memory Design Considerations
4. Intel® Stratix® 10 Embedded Memory IP References
5. Intel Stratix 10 Embedded Memory Design Example
6. Intel® Stratix® 10 Embedded Memory User Guide Archives
7. Document Revision History for the Intel® Stratix® 10 Embedded Memory User Guide
2.1. Byte Enable in Intel® Stratix® 10 Embedded Memory Blocks
2.2. Address Clock Enable Support
2.3. Asynchronous Clear and Synchronous Clear
2.4. Memory Blocks Error Correction Code Support
2.5. Force-to-Zero
2.6. Coherent Read Memory
2.7. Freeze Logic
2.8. True Dual Port Dual Clock Emulator
2.9. 'X' Propagation Support in Simulation
2.10. Intel® Stratix® 10 Supported Embedded Memory IPs
2.11. Intel® Stratix® 10 Embedded Memory Clocking Modes
2.12. Intel® Stratix® 10 Embedded Memory Configurations
2.13. Initial Value of Read and Write Address Registers
3.1. Consider the Memory Block Selection
3.2. Consider the Concurrent Read Behavior
3.3. Customize Read-During-Write Behavior
3.4. Consider Power-Up State and Memory Initialization
3.5. Reduce Power Consumption
3.6. Avoid Providing Non-Deterministic Input
3.7. Avoid Changing Clock Signals and Other Control Signals Simultaneously
3.8. Including the Reset Release Intel® FPGA IP in Your Design
4.1.1. Release Information for RAM and ROM Intel® FPGA IPs
4.1.2. RAM: 1-PORT Intel® FPGA IP Parameters
4.1.3. RAM: 2-PORT Intel® FPGA IP Parameters
4.1.4. RAM: 4-PORT Intel® FPGA IP Parameters
4.1.5. ROM: 1-PORT Intel® FPGA IP Parameters
4.1.6. ROM: 2-PORT Intel® FPGA IP Parameters
4.1.7. RAM and ROM Interface Signals
4.1.8. Changing Parameter Settings Manually
4.3.1. Release Information for FIFO Intel® FPGA IP
4.3.2. Configuration Methods
4.3.3. Specifications
4.3.4. FIFO Functional Timing Requirements
4.3.5. SCFIFO ALMOST_EMPTY Functional Timing
4.3.6. FIFO Output Status Flag and Latency
4.3.7. FIFO Metastability Protection and Related Options
4.3.8. FIFO Synchronous Clear and Asynchronous Clear Effect
4.3.9. SCFIFO and DCFIFO Show-Ahead Mode
4.3.10. Different Input and Output Width
4.3.11. DCFIFO Timing Constraint Setting
4.3.12. Coding Example for Manual Instantiation
4.3.13. Design Example
4.3.14. Gray-Code Counter Transfer at the Clock Domain Crossing
4.3.15. Guidelines for Embedded Memory ECC Feature
4.3.16. FIFO Intel® FPGA IP Parameters
4.3.17. Reset Scheme
4.4.1. Release Information for FIFO2 Intel® FPGA IP
4.4.2. Configuration Methods
4.4.3. Fmax Target Measuring Methodology
4.4.4. Performance Considerations
4.4.5. FIFO2 Intel® FPGA IP Features
4.4.6. FIFO2 Intel® FPGA IP Parameters
4.4.7. FIFO2 Intel® FPGA IP Interface Signals
4.4.8. Reset and Clock Schemes
4.5.1. Release Information for Shift Register (RAM-based) Intel® FPGA IP
4.5.2. Shift Register (RAM-based) Intel® FPGA IP Features
4.5.3. Shift Register (RAM-based) Intel® FPGA IP General Description
4.5.4. Shift Register (RAM-based) Intel® FPGA IP Parameter Settings
4.5.5. Shift Register Ports and Parameters Setting
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4.2.2.1. eSRAM Specifications
The following table summarizes the specifications of the eSRAM Intel® FPGA IP .
Feature | Detail | Value | Description |
---|---|---|---|
Clock Frequency 6 | -1 -2 -3 |
200 MHz - 750 MHz 200 MHz - 640 MHz
200 MHz - 500 MHz 7
|
— |
Bank Capacity | without ECC with ECC |
144 Kb 128 Kb |
Each bank is (2048) 2K x 72 bits |
Banks per Channel | — | 42 |
— |
Channel Capacity | without ECC with ECC |
5.90625 Mb 5.25 Mb |
— |
Channels per eSRAM | — | 8 |
— |
eSRAM Capacity | without ECC with ECC |
47.25 Mb 42 Mb |
— |
Interface Data Width | without ECC with ECC |
x72 |
Maximum width |
Read Latency 8 | Normal Low Power |
10 +2 9 11 + 2 9 |
These latencies are fixed, whether ECC is enabled or not. |
Write Latency | — | 0 +1 10 | There is a zero cycle latency for write commands issued to the eSRAM. |
Power (per eSRAM system) | Industrial Extended |
1.15 W - 1.5 W 2.28 W - 3.31 W |
Low Power mode to Normal mode. |
6 The input clock source for eSRAM must not exceed 20 ps peak-to-peak, or 1.42 ps RMS at 1e-12 BER, 1.22 ps at 1e-16 BER.
7 In Speed Grade 3 devices, the following clock frequency range is not supported:
- 466.51 MHz - 499.99 MHz
- 233.26 MHz - 249.99 MHz
8 Read latency is measured from a read command being presented to the interface to valid read data being returned.
9 +2 on read latency is added due to registers interfacing with eSRAM required to meet routing and timing requirement.
10 +1 on read latency is added due to registers interfacing with eSRAM required to meet routing and timing requirement.