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1. Intel® Stratix® 10 Embedded Memory Overview
2. Intel® Stratix® 10 Embedded Memory Architecture and Features
3. Intel® Stratix® 10 Embedded Memory Design Considerations
4. Intel® Stratix® 10 Embedded Memory IP References
5. Intel Stratix 10 Embedded Memory Design Example
6. Intel® Stratix® 10 Embedded Memory User Guide Archives
7. Document Revision History for the Intel® Stratix® 10 Embedded Memory User Guide
2.1. Byte Enable in Intel® Stratix® 10 Embedded Memory Blocks
2.2. Address Clock Enable Support
2.3. Asynchronous Clear and Synchronous Clear
2.4. Memory Blocks Error Correction Code Support
2.5. Force-to-Zero
2.6. Coherent Read Memory
2.7. Freeze Logic
2.8. True Dual Port Dual Clock Emulator
2.9. 'X' Propagation Support in Simulation
2.10. Intel® Stratix® 10 Supported Embedded Memory IPs
2.11. Intel® Stratix® 10 Embedded Memory Clocking Modes
2.12. Intel® Stratix® 10 Embedded Memory Configurations
2.13. Initial Value of Read and Write Address Registers
3.1. Consider the Memory Block Selection
3.2. Consider the Concurrent Read Behavior
3.3. Customize Read-During-Write Behavior
3.4. Consider Power-Up State and Memory Initialization
3.5. Reduce Power Consumption
3.6. Avoid Providing Non-Deterministic Input
3.7. Avoid Changing Clock Signals and Other Control Signals Simultaneously
3.8. Including the Reset Release Intel® FPGA IP in Your Design
4.1.1. Release Information for RAM and ROM Intel® FPGA IPs
4.1.2. RAM: 1-PORT Intel® FPGA IP Parameters
4.1.3. RAM: 2-PORT Intel® FPGA IP Parameters
4.1.4. RAM: 4-PORT Intel® FPGA IP Parameters
4.1.5. ROM: 1-PORT Intel® FPGA IP Parameters
4.1.6. ROM: 2-PORT Intel® FPGA IP Parameters
4.1.7. RAM and ROM Interface Signals
4.1.8. Changing Parameter Settings Manually
4.3.1. Release Information for FIFO Intel® FPGA IP
4.3.2. Configuration Methods
4.3.3. Specifications
4.3.4. FIFO Functional Timing Requirements
4.3.5. SCFIFO ALMOST_EMPTY Functional Timing
4.3.6. FIFO Output Status Flag and Latency
4.3.7. FIFO Metastability Protection and Related Options
4.3.8. FIFO Synchronous Clear and Asynchronous Clear Effect
4.3.9. SCFIFO and DCFIFO Show-Ahead Mode
4.3.10. Different Input and Output Width
4.3.11. DCFIFO Timing Constraint Setting
4.3.12. Coding Example for Manual Instantiation
4.3.13. Design Example
4.3.14. Gray-Code Counter Transfer at the Clock Domain Crossing
4.3.15. Guidelines for Embedded Memory ECC Feature
4.3.16. FIFO Intel® FPGA IP Parameters
4.3.17. Reset Scheme
4.4.1. Release Information for FIFO2 Intel® FPGA IP
4.4.2. Configuration Methods
4.4.3. Fmax Target Measuring Methodology
4.4.4. Performance Considerations
4.4.5. FIFO2 Intel® FPGA IP Features
4.4.6. FIFO2 Intel® FPGA IP Parameters
4.4.7. FIFO2 Intel® FPGA IP Interface Signals
4.4.8. Reset and Clock Schemes
4.5.1. Release Information for Shift Register (RAM-based) Intel® FPGA IP
4.5.2. Shift Register (RAM-based) Intel® FPGA IP Features
4.5.3. Shift Register (RAM-based) Intel® FPGA IP General Description
4.5.4. Shift Register (RAM-based) Intel® FPGA IP Parameter Settings
4.5.5. Shift Register Ports and Parameters Setting
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4.2.4. eSRAM Intel® FPGA IP Interface Signals
The following table lists the input and output signals of the eSRAM Intel® FPGA IP interface.
Signal | Direction | Width | Description |
---|---|---|---|
refclk | Input | 1 | Provide a PLL reference clock. This clock must be stable and free-running at device power-up for a successful configuration. |
esram2f_clk | Output | 1 | Core clock provided by the eSRAM to the fabric. Use this clock to drive core logics that are interfacing with the eSRAM. Otherwise, proper cross-clock domain circuitry is expected. |
c<channel_number>_data_0 | Input | 1-72 |
|
c<channel_number>_wraddress_0 | Input | Range from 17–11 |
Write address of the memory. Dependent on how many banks are enabled in the channel.
Note: Writing to an invalid address does nothing, because the targeted bank is not powered.
|
c<channel_number>_wren_n_0 | Input | 1 | Active low write enable input for the wraddress port. |
c<channel_number>_rdaddress_0 | Input | Range from 17–11 |
Read address of the memory. Dependent on how many banks are enabled in the channel.
Note: If you attempt to read from an invalid address, the data returned is random and of no value.
|
c<channel_number>_rden_n_0 | Input | 1 | Active low read enable input for the rdaddress port. |
c<channel_number>_q_0 | Output | 72 or 64 |
|
ECC Enabled | |||
c<channel_number>_error_detect_0 | Output | 1 | Asserts when an ECC error occurred on the read data retrieved from the eSRAM. |
c<channel_number>_error_correct_0 | Output | 1 | Asserts when an ECC error is successfully corrected. The memory content is not updated with the corrected data. |
Dynamic ECC Bypass Enabled | |||
c<channel_number>_eccencbypass_0 | Input | 1 | Dynamically bypass the ECC Encoder. When active, this port allows user to inject parity bits through 8-bits MSB from data port (c<channel_number>_data_0[71:64]). When inactive, parity bits will be generated using internal ECC Encoder. This port can only be used when c<channel_number>_ecc_byp_enable parameter is set to "TRUE". |
c<channel_number>_eccdecbypass_0 | Input | 1 | Dynamically bypass the ECC Decoder. 8-bits MSB from output port (c<channel_number>_q_0[73:64]) represents the parity bits. Parity bits are not checked and the c<channel_number>_error_detect_0 and c<channel_number>_error_correct_0 signals should not assert. This port can only be used when c<channel_number>_ecc_byp_enable parameter is set to "TRUE". |
Additional Options | |||
c<channel_number>_sd_n_0 | Input | 1 | Active low signal that dynamically shuts down channels. This signal shuts down power to periphery (active low) and memory core of the banks within the channel, with no memory data retention. In addition to the channels that are statically shut down when choosing the number of channels to use in an eSRAM system, you can also dynamically shut down channels at run time.
Note: Memory contents are not retained when a channel is shut down.
|
iopll_lock2core | Output | 1 | eSRAM IOPLL lock status.
|