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1. About the Video and Vision Processing Suite
2. Getting Started with the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description
4. Video and Vision Processing IP Interfaces
5. Video and Vision Processing IP Registers
6. Video and Vision Processing IPs Software Programming Model
7. Protocol Converter Intel® FPGA IP
8. 1D LUT Intel® FPGA IP
9. 3D LUT Intel® FPGA IP
10. AXI-Stream Broadcaster Intel® FPGA IP
11. Bits per Color Sample Adapter Intel FPGA IP
12. Black Level Correction Intel® FPGA IP
13. Black Level Statistics Intel® FPGA IP
14. Chroma Key Intel® FPGA IP
15. Chroma Resampler Intel® FPGA IP
16. Clipper Intel® FPGA IP
17. Clocked Video Input Intel® FPGA IP
18. Clocked Video to Full-Raster Converter Intel® FPGA IP
19. Clocked Video Output Intel® FPGA IP
20. Color Space Converter Intel® FPGA IP
21. Defective Pixel Correction Intel® FPGA IP
22. Deinterlacer Intel® FPGA IP
23. Demosaic Intel® FPGA IP
24. FIR Filter Intel® FPGA IP
25. Frame Cleaner Intel® FPGA IP
26. Full-Raster to Clocked Video Converter Intel® FPGA IP
27. Full-Raster to Streaming Converter Intel® FPGA IP
28. Genlock Controller Intel® FPGA IP
29. Generic Crosspoint Intel® FPGA IP
30. Genlock Signal Router Intel® FPGA IP
31. Guard Bands Intel® FPGA IP
32. Histogram Statistics Intel® FPGA IP
33. Interlacer Intel® FPGA IP
34. Mixer Intel® FPGA IP
35. Pixels in Parallel Converter Intel® FPGA IP
36. Scaler Intel® FPGA IP
37. Stream Cleaner Intel® FPGA IP
38. Switch Intel® FPGA IP
39. Tone Mapping Operator Intel® FPGA IP
40. Test Pattern Generator Intel® FPGA IP
41. Unsharp Mask Intel® FPGA IP
42. Video and Vision Monitor Intel FPGA IP
43. Video Frame Buffer Intel® FPGA IP
44. Video Frame Reader Intel FPGA IP
45. Video Frame Writer Intel FPGA IP
46. Video Streaming FIFO Intel® FPGA IP
47. Video Timing Generator Intel® FPGA IP
48. Vignette Correction Intel® FPGA IP
49. Warp Intel® FPGA IP
50. White Balance Correction Intel® FPGA IP
51. White Balance Statistics Intel® FPGA IP
52. Design Security
53. Document Revision History for Video and Vision Processing Suite User Guide
28.4.1. Achieving Genlock Controller Free Running (for Initialization or from Lock to Reference Clock N)
28.4.2. Locking to Reference Clock N (from Genlock Controller IP free running)
28.4.3. Setting the VCXO hold over
28.4.4. Restarting the Genlock Controller IP
28.4.5. Locking to Reference Clock N New (from Locking to Reference Clock N Old)
28.4.6. Changing to Reference Clock or VCXO Base Frequencies (switch between p50 and p59.94 video formats and vice-versa)
28.4.7. Disturbing a Reference Clock (a cable pull)
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25.3. Frame Cleaner IP Functional Description
When using the full variant of the protocol, the expected field width and height are in the image information packets that precede each field. When using the lite variant, you specify the field width and height to the Frame Cleaner IP via the register map.
In both variants of the protocol, the video fields may have too few or too many pixels in each line packet compared to the specified field width. Each line packet can even contain a different number of pixels, which does not violate the protocol specification. For line packets with too many pixels, the IP clips the surplus beats of data. For line packets with too few pixels, extra beats of data are appended to the packet to match the expected number of pixels.
Video fields may also have too few or too many line packets compared to the specified field height. For fields with too many line packets, the extra packets are discarded. For fields with too few packets, additional packets are added after the last input packet to match the expected length.
When the Frame Cleaner IP creates extra pixel data the value used is always the same. The most significant bit of each color plane is set to ‘1’ and all other bits are set to ‘0’. The IP uses this value as it displays as a similar light grey color in the RGB, YCbCr and monochrome color spaces.
Backpressure and Overflow
When the Frame Cleaner IP receives fields that have fewer pixels per line than expected it must add additional pixels at the end of the line packet. When it receives fields with fewer line packets than expected it must insert additional line packets into the stream. In both cases, to allow the extra pixels to be inserted into the stream, the IP must lower the tready signal on the input interface and create backpressure. If the disparity between the expected and received width or height is small, this additional backpressure may be absorbed by the blanking in the incoming video (if any exists). However, if the disparity is larger (or there is no blanking in the incoming video), the large periods of backpressure can force video sources that you can't stall (such as HDMI) to drop data (overflow).
The loss of data at the input is an undesirable (if unavoidable) consequence of padding fields to match and expected size. However, the additional backpressure might create a positive feedback loop that leads to continuous overflow. In this case, a shorter than expected input field results in padding and backpressure. The input continues to receive the next field, but the backpressure causes overflow, which typically causes the input IP to terminate the stream for the input field earlier than expected. The Frame Cleaner IP is then forced to apply padding to this field, which creates more backpressure and the cycle repeats.
To avoid hitting this overflow feedback condition, only use the Frame Cleaner IP with video sources than can either accept backpressure (and reduce the video rate), or that can detect (and signal) an overflow condition that the system controller can pause.
Maximum and minimum field size restrictions
When you write IPs for video processing you may want to restrict the maximum and or minimum field sizes that they can process to save resources and improve clock speed. For example, the IPs in the Intel Video and Vision Processing Suite can process fields as small as one pixel wide and or high. However, while the Intel FPGA Streaming Video protocol allows for fields with widths and or heights up to 65536 pixels, the majority of the Intel Video and Vision Processing Suite IPs only support widths and heights up to 16384 pixels. The IPs do not hang if they receive fields that are too large, but the output field is not processed in the manner expected.
When using the Frame Cleaner IP with the Lite variant of the Intel FPGA Streaming Video protocol, the field width and height are configured via the register map. As you control the values you write to the register map, you can enforce any minimum or maximum field size restrictions in software by limiting the values you write. The Frame Cleaner IP accepts the values in the register map and the output fields are always bound by the maximum and minimum values.
When using the Frame Cleaner with the Full variant of the Intel FPGA Streaming Video, the field dimensions are specified by the incoming image information packets. Typically, you may not have full control over the width and height values sent by upstream IPs, the image information packets in the stream may not adhere to any minimum or maximum frame size requirements for downstream IPs. For this reason, with full variant Frame Cleaner IPs, you can enforce user-set maximum and minimum width and height values. When you turn on Custom resolution limits, the IP edits any incoming image information packet with a height or width value that falls outside the specified range to the appropriate maximum or minimum value. The IP pads or crops accompanying field as appropriate to match the values in the outgoing image information packet.
Control Agent Interface
For lite variant Frame Cleaner IPs, you must turn on the Avalon memory-mapped control agent interface so you can set the expected field height and width values. For full variants of the Frame Cleaner, the IP takes these values from the incoming image information packets. The Frame Cleaner IP has no other runtime editable settings, so the control agent interface is not required with full variants (but may still be on if you turn on Debug features during parametrization).
The Frame Cleaner IP can count the number of error conditions encountered and report these values via the register map to assist with debugging. This feature is only on if you turn on Debug features.