Video and Vision Processing Suite Intel® FPGA IP User Guide

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ID 683329
Date 12/31/2023
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Document Table of Contents
Document Table of Contents x
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. AXI-Stream Broadcaster Intel® FPGA IP 11. Bits per Color Sample Adapter Intel FPGA IP 12. Black Level Correction Intel® FPGA IP 13. Black Level Statistics Intel® FPGA IP 14. Chroma Key Intel® FPGA IP 15. Chroma Resampler Intel® FPGA IP 16. Clipper Intel® FPGA IP 17. Clocked Video Input Intel® FPGA IP 18. Clocked Video to Full-Raster Converter Intel® FPGA IP 19. Clocked Video Output Intel® FPGA IP 20. Color Space Converter Intel® FPGA IP 21. Defective Pixel Correction Intel® FPGA IP 22. Deinterlacer Intel® FPGA IP 23. Demosaic Intel® FPGA IP 24. FIR Filter Intel® FPGA IP 25. Frame Cleaner Intel® FPGA IP 26. Full-Raster to Clocked Video Converter Intel® FPGA IP 27. Full-Raster to Streaming Converter Intel® FPGA IP 28. Genlock Controller Intel® FPGA IP 29. Generic Crosspoint Intel® FPGA IP 30. Genlock Signal Router Intel® FPGA IP 31. Guard Bands Intel® FPGA IP 32. Histogram Statistics Intel® FPGA IP 33. Interlacer Intel® FPGA IP 34. Mixer Intel® FPGA IP 35. Pixels in Parallel Converter Intel® FPGA IP 36. Scaler Intel® FPGA IP 37. Stream Cleaner Intel® FPGA IP 38. Switch Intel® FPGA IP 39. Tone Mapping Operator Intel® FPGA IP 40. Test Pattern Generator Intel® FPGA IP 41. Unsharp Mask Intel® FPGA IP 42. Video and Vision Monitor Intel FPGA IP 43. Video Frame Buffer Intel® FPGA IP 44. Video Frame Reader Intel FPGA IP 45. Video Frame Writer Intel FPGA IP 46. Video Streaming FIFO Intel® FPGA IP 47. Video Timing Generator Intel® FPGA IP 48. Vignette Correction Intel® FPGA IP 49. Warp Intel® FPGA IP 50. White Balance Correction Intel® FPGA IP 51. White Balance Statistics Intel® FPGA IP 52. Design Security 53. Document Revision History for Video and Vision Processing Suite User Guide
1. About the Video and Vision Processing Suite x
1.1. Video and Vision Processing IPs Features 1.2. Device Family Support 1.3. Video and Vision Processing IPs Release Information 1.4. Lite versus Full IP Variants 1.5. Glossary of Video and Vision Terminology
2. Getting Started with the Video and Vision Processing IPs x
2.1. Video and Vision Processing IP Evaluation Time-out Behavior 2.2. Generating a Video and Vision Processing IP 2.3. Simulating the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description x
3.1. Auxiliary Control Packets 3.2. Latency 3.3. IP Debugging Features 3.4. Stall Behavior and Error Recovery 3.5. Avalon Streaming Video Protocol Versus Intel FPGA Streaming Video Protocol
5. Video and Vision Processing IP Registers x
5.1. Video and Vision Processing IP Control Examples
7. Protocol Converter Intel® FPGA IP x
7.1. About the Protocol Converter IP 7.2. Protocol Converter IP Parameters 7.3. Protocol Converter IP Functional Description 7.4. Protocol Converter IP Interfaces 7.5. Protocol Converter IP Registers 7.6. Protocol Converter IP Software API
7.1. About the Protocol Converter IP x
7.1.1. Protocol Converter IP Performance and Resources
8. 1D LUT Intel® FPGA IP x
8.1. About the 1D LUT IP 8.2. 1D LUT IP Parameters 8.3. 1D LUT IP Interfaces 8.4. 1D LUT IP Registers 8.5. 1D LUT IP Software API
8.1. About the 1D LUT IP x
8.1.1. 1D LUT IP Performance and Resources
9. 3D LUT Intel® FPGA IP x
9.1. About the 3D LUT Intel® FPGA IP 9.2. 3D LUT IP Parameters 9.3. 3D LUT IP Block Description 9.4. 3D LUT IP Registers 9.5. 3D LUT IP Software API
9.1. About the 3D LUT Intel® FPGA IP x
9.1.1. 3D LUT IP Features 9.1.2. 3D LUT IP Performance IP and Resource Information
9.3. 3D LUT IP Block Description x
9.3.1. 3D LUT IP Interfaces 9.3.2. 3D LUT IP Latency
10. AXI-Stream Broadcaster Intel® FPGA IP x
10.1. About the AXI-Stream Broadcaster IP 10.2. AXI-Stream Broadcaster IP Parameters 10.3. AXI-Stream Broadcaster IP Interfaces
10.1. About the AXI-Stream Broadcaster IP x
10.1.1. AXI-Stream Broadcaster IP Features 10.1.2. AXI-Stream Broadcaster IP Performance and Resources
11. Bits per Color Sample Adapter Intel FPGA IP x
11.1. About the Bits per Color Sample Adapter IP 11.2. Bits per Color Sample Adapter IP Parameters 11.3. Bits per Color Sample Adapter IP Interfaces 11.4. Bits per Color Sample Adapter IP Registers 11.5. Bits per Color Sample Adapter Software API
11.1. About the Bits per Color Sample Adapter IP x
11.1.1. Bits per Color Sample Adapter IP Performance and Resources
12. Black Level Correction Intel® FPGA IP x
12.1. About the Black Level Correction IP 12.2. Black Level Correction IP Parameters 12.3. Black Level Correction IP Functional Description 12.4. Black Level Correction IP Registers 12.5. Black Level Correction IP Software API
12.1. About the Black Level Correction IP x
12.1.1. Black Level Correction IP Performance and Resources
12.3. Black Level Correction IP Functional Description x
12.3.1. Black Level Correction IP Interfaces
13. Black Level Statistics Intel® FPGA IP x
13.1. About the Black Level Statistics IP 13.2. Black Level Statistics IP Parameters 13.3. Black Level Statistics IP Interfaces 13.4. Black Level Statistics IP Registers 13.5. Black Level Statistics IP Software API
13.1. About the Black Level Statistics IP x
13.1.1. Black Level Statistics IP Performance and Resources
14. Chroma Key Intel® FPGA IP x
14.1. About the Chroma Key IP 14.2. Chroma Key IP Parameters 14.3. Chroma Key IP Interfaces 14.4. Chroma Key Replacement 14.5. Chroma Key IP Registers 14.6. Chroma Key IP Software API
14.1. About the Chroma Key IP x
14.1.1. Chroma Key IP Performance and Resources
15. Chroma Resampler Intel® FPGA IP x
15.1. About the Chroma Resampler IP 15.2. Chroma Resampler IP Parameters 15.3. Chroma Resampler IP Functional Description 15.4. Chroma Resampler IP Registers 15.5. Chroma Resampler IP Software API
15.1. About the Chroma Resampler IP x
15.1.1. Chroma Resampler Performance and Resources
15.3. Chroma Resampler IP Functional Description x
15.3.1. Chroma Resampler IP Interfaces
16. Clipper Intel® FPGA IP x
16.1. About the Clipper IP 16.2. Clipper IP Parameters 16.3. Clipper IP Interfaces 16.4. Clipper IP Registers 16.5. Clipper IP Software API
16.1. About the Clipper IP x
16.1.1. Clipper IP Performance and Resources
17. Clocked Video Input Intel® FPGA IP x
17.1. About the Clocked Video Input IP 17.2. Initializing the Clocked Video Input IP 17.3. Clocked Video Input IP Parameters 17.4. Clocked Video Input IP Interfaces 17.5. Clocked Video Input IP Registers 17.6. Clocked Video Input IP Software API
17.1. About the Clocked Video Input IP x
17.1.1. Clocked Video Input IP Features 17.1.2. Clocked Video Input IP Performance and Resources
18. Clocked Video to Full-Raster Converter Intel® FPGA IP x
18.1. About the Clocked Video to Full-Raster Converter IP 18.2. Clocked Video to Full-Raster Converter Parameters 18.3. Clocked Video to Full-Raster Converter Block Description 18.4. Clocked Video Converter to Full-Raster IP Registers
18.1. About the Clocked Video to Full-Raster Converter IP x
18.1.1. Clocked Video to Full-Raster Converter Features 18.1.2. Clocked Video to Full-Raster Converter Performance and Resources
18.3. Clocked Video to Full-Raster Converter Block Description x
18.3.1. Clocked Video to Full-Raster Converter Interfaces
19. Clocked Video Output Intel® FPGA IP x
19.1. About the Clocked Video Output IP 19.2. Clocked Video Output IP Parameters 19.3. Clocked Video Output IP Functional Description 19.4. Clocked Video Output IP Interfaces 19.5. Clocked Video Output IP Registers 19.6. Clocked Video Output IP Software API
19.1. About the Clocked Video Output IP x
19.1.1. Clocked Video Output IP Performance and Resources 19.1.2. Clocked Video Output IP Features
20. Color Space Converter Intel® FPGA IP x
20.1. About the Color Space Converter IP 20.2. Color Space Converter IP Parameters 20.3. Color Space Converter IP Functional Description 20.4. Color Space Converter IP Registers 20.5. Color Space Converter IP Software API
20.1. About the Color Space Converter IP x
20.1.1. Color Space Converter IP Features 20.1.2. Color Space Converter IP Performance and Resources
20.3. Color Space Converter IP Functional Description x
20.3.1. Color Space Converter IP Interfaces
21. Defective Pixel Correction Intel® FPGA IP x
21.1. About the Defective Pixel Correction IP 21.2. Defective Pixel Correction IP Parameters 21.3. Defective Pixel Correction IP Functional Description 21.4. Defective Pixel Correction IP Registers 21.5. Defective Pixel Correction IP Software API
21.1. About the Defective Pixel Correction IP x
21.1.1. Defective Pixel Correction IP Performance and Resources
21.3. Defective Pixel Correction IP Functional Description x
21.3.1. Defective Pixel Correction IP Interfaces
22. Deinterlacer Intel® FPGA IP x
22.1. About the Deinterlacer IP 22.2. Deinterlacer Parameters 22.3. Deinterlacer Interfaces 22.4. Deinterlacer IP Registers 22.5. Deinterlacer IP Software API
22.1. About the Deinterlacer IP x
22.1.1. Deinterlacer Performance and Resources
23. Demosaic Intel® FPGA IP x
23.1. About the Demosaic IP 23.2. Demosaic IP Parameters 23.3. Demosaic IP Functional Description 23.4. Demosaic IP Registers 23.5. Demosaic IP Software API
23.1. About the Demosaic IP x
23.1.1. Demosaic IP Performance and Resources
23.3. Demosaic IP Functional Description x
23.3.1. Demosaic IP Interfaces
24. FIR Filter Intel® FPGA IP x
24.1. About the FIR Filter 24.2. FIR Filter Parameters 24.3. FIR Filter IP Operation 24.4. FIR Filter Interfaces 24.5. FIR Filter Registers 24.6. FIR Filter IP Software API
24.1. About the FIR Filter x
24.1.1. FIR Filter IP Performance and Resources
24.3. FIR Filter IP Operation x
24.3.1. FIR Filter Processing 24.3.2. FIR Filter Precision 24.3.3. FIR Coefficient Specification 24.3.4. FIR Filter Symmetry 24.3.5. Result to Output Data Type Conversion
24.3.4. FIR Filter Symmetry x
24.3.4.1. No Symmetry 24.3.4.2. Horizontal Symmetry 24.3.4.3. Vertical Symmetry 24.3.4.4. Horizontal and Vertical Symmetry 24.3.4.5. Diagonal Symmetry
25. Frame Cleaner Intel® FPGA IP x
25.1. About the Frame Cleaner IP 25.2. Frame Cleaner IP Parameters 25.3. Frame Cleaner IP Functional Description 25.4. Frame Cleaner IP Interfaces 25.5. Frame Cleaner IP Registers 25.6. Frame Cleaner IP Software API
25.1. About the Frame Cleaner IP x
25.1.1. Frame Cleaner IP Performance and Resources
26. Full-Raster to Clocked Video Converter Intel® FPGA IP x
26.1. About the Full-Raster to Clocked Video Converter 26.2. Full Raster to Clocked Video Converter Parameters 26.3. Full-Raster to Clocked Video Converter Block Description 26.4. Full-Raster to Clocked Video Converter Registers
26.1. About the Full-Raster to Clocked Video Converter x
26.1.1. Full-Raster to Clocked Video Converter Features 26.1.2. Full-Raster to Clocked Video Converter Performance and Resource Utilization
26.3. Full-Raster to Clocked Video Converter Block Description x
26.3.1. Full Raster to Clocked Video Converter Interfaces
27. Full-Raster to Streaming Converter Intel® FPGA IP x
27.1. About the Full-Raster to Streaming Converter IP 27.2. Full-Raster to Streaming Converter Parameters 27.3. Full-Raster to Streaming Converter Block Description
27.1. About the Full-Raster to Streaming Converter IP x
27.1.1. Full-Raster to Streaming Converter Features 27.1.2. Full-Raster to Streaming Converter Performance and Resources
27.3. Full-Raster to Streaming Converter Block Description x
27.3.1. Full-Raster to Streaming Converter Interfaces
28. Genlock Controller Intel® FPGA IP x
28.1. About the Genlock Controller IP 28.2. Genlock Controller IP Parameters 28.3. Genlock Controller IP Functional Description 28.4. Using Genlock Controller IP Software 28.5. Genlock Controller IP Registers 28.6. Genlock Controller IP Software API
28.1. About the Genlock Controller IP x
28.1.1. Genlock Controller IP Performance and Resources
28.3. Genlock Controller IP Functional Description x
28.3.1. Genlock Controller IP Interfaces
28.4. Using Genlock Controller IP Software x
28.4.1. Achieving Genlock Controller Free Running (for Initialization or from Lock to Reference Clock N) 28.4.2. Locking to Reference Clock N (from Genlock Controller IP free running) 28.4.3. Setting the VCXO hold over 28.4.4. Restarting the Genlock Controller IP 28.4.5. Locking to Reference Clock N New (from Locking to Reference Clock N Old) 28.4.6. Changing to Reference Clock or VCXO Base Frequencies (switch between p50 and p59.94 video formats and vice-versa) 28.4.7. Disturbing a Reference Clock (a cable pull)
29. Generic Crosspoint Intel® FPGA IP x
29.1. About the Generic Crosspoint IP 29.2. Generic Crosspoint IP Parameters 29.3. Generic Crosspoint IP Interfaces 29.4. Generic Crosspoint IP Registers 29.5. Generic Crosspoint IP Software API
29.1. About the Generic Crosspoint IP x
29.1.1. Generic Crosspoint IP Features 29.1.2. Generic Crosspoint Performance and Resources
30. Genlock Signal Router Intel® FPGA IP x
30.1. About the Genlock Signal Router IP 30.2. Genlock Signal Router IP Parameters 30.3. Genlock Signal Router IP Interfaces 30.4. Genlock Signal Router IP Registers 30.5. Genlock Signal Router IP Software API
30.1. About the Genlock Signal Router IP x
30.1.1. Genlock Signal Router IP Features 30.1.2. Genlock Signal Router IP Performance and Resources
31. Guard Bands Intel® FPGA IP x
31.1. About the Guard Bands IP 31.2. Guard Bands IP Parameters 31.3. Guard Bands IP Interfaces 31.4. Guard Bands IP Registers 31.5. Guard Bands IP Software API
31.1. About the Guard Bands IP x
31.1.1. Guard Bands IP Performance and Resources
32. Histogram Statistics Intel® FPGA IP x
32.1. About the Histogram Statistics IP 32.2. Histogram Statistics IP Parameters 32.3. Histogram Statistics IP Interfaces 32.4. Histogram Statistics IP Registers 32.5. Histogram Statistics IP Software API
32.1. About the Histogram Statistics IP x
32.1.1. Histogram Statistics IP Performance and Resources
33. Interlacer Intel® FPGA IP x
33.1. About the Interlacer IP 33.2. Interlacer IP Parameters 33.3. Interlacer IP Functional Description 33.4. Interlacer IP Registers 33.5. Interlacer IP Software API
33.1. About the Interlacer IP x
33.1.1. Interlacer IP Performance and Resources
33.3. Interlacer IP Functional Description x
33.3.1. Interlacer IP Interfaces
34. Mixer Intel® FPGA IP x
34.1. About the Mixer IP 34.2. Mixer IP Parameters 34.3. Mixer IP Functional Description 34.4. Mixer IP Registers 34.5. Mixer IP Software API
34.1. About the Mixer IP x
34.1.1. Mixer IP Performance and Resources
34.3. Mixer IP Functional Description x
34.3.1. Mixer IP Interfaces
35. Pixels in Parallel Converter Intel® FPGA IP x
35.1. About the Pixels in Parallel Converter IP 35.2. Pixels in Parallel Converter IP Parameters 35.3. Pixels in Parallel Converter Interfaces 35.4. Pixels in Parallel Converter Registers 35.5. Pixels in Parallel Converter IP Software API
35.1. About the Pixels in Parallel Converter IP x
35.1.1. Pixels in Parallel Converter IP Performance and Resources
36. Scaler Intel® FPGA IP x
36.1. About the Scaler 36.2. Scaler IP Parameters 36.3. Scaler IP Functional Description 36.4. Scaler IP Registers 36.5. Scaler IP Software API
36.1. About the Scaler x
36.1.1. Scaler IP Performance and Resources
36.2. Scaler IP Parameters x
36.2.1. Scaler Maximum Resolution
36.3. Scaler IP Functional Description x
36.3.1. Coefficient Selection 36.3.2. Coefficient Quantization 36.3.3. Filter Behavior at Edge Boundaries 36.3.4. Partial Frame Scaling 36.3.5. 422 and 420 Chroma Sampled Data Scaling 36.3.6. Scaler IP Interfaces
36.3.1. Coefficient Selection x
36.3.1.1. Updating Scaler IP Runtime Coefficients
37. Stream Cleaner Intel® FPGA IP x
37.1. About the Stream Cleaner IP 37.2. Stream Cleaner IP Parameters 37.3. Stream Cleaner IP Functional Description
37.1. About the Stream Cleaner IP x
37.1.1. Stream Cleaner IP Performance and Resources
37.3. Stream Cleaner IP Functional Description x
37.3.1. Stream Cleaner IP Interfaces
38. Switch Intel® FPGA IP x
38.1. About the Switch IP 38.2. Switch IP Parameters 38.3. Switch IP Functional Description 38.4. Switch IP Registers 38.5. Switch IP Software API
38.1. About the Switch IP x
38.1.1. Switch IP Performance and Resources
38.3. Switch IP Functional Description x
38.3.1. Switch IP Latency 38.3.2. Switch IP Interfaces
39. Tone Mapping Operator Intel® FPGA IP x
39.1. About the Tone Mapping Operator IP 39.2. TMO IP Parameters 39.3. TMO IP Block Description 39.4. TMO IP Registers 39.5. TMO IP Software API
39.1. About the Tone Mapping Operator IP x
39.1.1. TMO IP Features 39.1.2. TMO IP Performance and Resource Utilization
39.3. TMO IP Block Description x
39.3.1. TMO IP Interfaces 39.3.2. TMO IP Latency
40. Test Pattern Generator Intel® FPGA IP x
40.1. About the Test Pattern Generator IP 40.2. Test Pattern Generator IP Parameters 40.3. Test Pattern Generator IP Functional Description 40.4. Test Pattern Generator IP Registers 40.5. Test Pattern Generator IP Software API
40.1. About the Test Pattern Generator IP x
40.1.1. Test Pattern Generator IP Performance and Resources
40.3. Test Pattern Generator IP Functional Description x
40.3.1. Test Pattern Generator IP Interfaces
41. Unsharp Mask Intel® FPGA IP x
41.1. About the Unsharp Mask IP 41.2. Unsharp Mask IP Parameters 41.3. Unsharp Mask IP Functional Description 41.4. Unsharp Mask IP Registers 41.5. Unsharp Mask IP Software API
41.1. About the Unsharp Mask IP x
41.1.1. Unsharp Mask IP Performance and Resources
41.3. Unsharp Mask IP Functional Description x
41.3.1. Unsharp Mask IP Interfaces
42. Video and Vision Monitor Intel FPGA IP x
42.1. About the Video and Vision Monitor IP 42.2. Video and Vision Monitor IP Parameters 42.3. Video and Vision Monitor IP Functional Description 42.4. Video and Vision Monitor IP Registers 42.5. Video and Vision Monitor Software API
42.1. About the Video and Vision Monitor IP x
42.1.1. Video and Vision Monitor IP Performance and Resources
42.3. Video and Vision Monitor IP Functional Description x
42.3.1. Video and Vision Monitor IP Interfaces
43. Video Frame Buffer Intel® FPGA IP x
43.1. About the Video Frame Buffer IP 43.2. Video Frame Buffer IP Parameters 43.3. Video Frame Buffer IP Functional Description 43.4. Video Frame Buffer IP Registers 43.5. Video Frame Buffer IP Software API
43.1. About the Video Frame Buffer IP x
43.1.1. Video Frame Buffer Performance and Resources
43.3. Video Frame Buffer IP Functional Description x
43.3.1. Video Frame Buffer IP Interfaces
44. Video Frame Reader Intel FPGA IP x
44.1. About the Video Frame Reader IP 44.2. Video Frame Reader IP Parameters 44.3. Video Frame Reader IP Functional Description 44.4. Video Frame Reader IP Registers 44.5. Video Frame Reader IP Software API
44.1. About the Video Frame Reader IP x
44.1.1. Video Frame Reader IP Performance and Resources
44.3. Video Frame Reader IP Functional Description x
44.3.1. Video Frame Reader IP Interfaces
45. Video Frame Writer Intel FPGA IP x
45.1. About the Video Buffer Writer IP 45.2. Video Frame Writer IP Parameters 45.3. Video Frame Writer IP Functional Description 45.4. Video Frame Writer IP Registers 45.5. Video Frame Writer IP Software API
45.1. About the Video Buffer Writer IP x
45.1.1. Video Frame Writer IP Performance and Resources
45.3. Video Frame Writer IP Functional Description x
45.3.1. Video Frame Writer IP Interfaces
46. Video Streaming FIFO Intel® FPGA IP x
46.1. About the Video Streaming FIFO IP 46.2. Video Streaming FIFO IP Parameters 46.3. Video Streaming FIFO IP Interfaces
46.1. About the Video Streaming FIFO IP x
46.1.1. Video Streaming FIFO IP Performance and Resources
47. Video Timing Generator Intel® FPGA IP x
47.1. About the Video Timing Generator IP 47.2. Video Timing Generator IP Parameters 47.3. Video Timing Generator IP Functional Description 47.4. Video Timing Generator IP Interfaces 47.5. Video Timing Generator IP Registers 47.6. Video Timing Generator IP Software API
47.1. About the Video Timing Generator IP x
47.1.1. Video Timing Generator IP Features 47.1.2. Video Timing Generator IP Performance and Resources
48. Vignette Correction Intel® FPGA IP x
48.1. About the Vignette Correction IP 48.2. Vignette Correction IP Parameters 48.3. Vignette Correction IP Interfaces 48.4. Vignette Correction IP Registers 48.5. Vignette Correction IP Software API
48.1. About the Vignette Correction IP x
48.1.1. Vignette Correction IP Performance and Resources
49. Warp Intel® FPGA IP x
49.1. About the Warp IP 49.2. Warp IP Parameters 49.3. Warp IP Block Description 49.4. Warp IP Registers 49.5. Warp IP Software API
49.1. About the Warp IP x
49.1.1. Warp IP Features 49.1.2. Warp IP Performance and Resource Utilization
49.3. Warp IP Block Description x
49.3.1. Block Cache Tool 49.3.2. Warp IP Interfaces 49.3.3. Warp IP Latency 49.3.4. External Memory for Warp IP Memory Space Allocation in External Memory Bandwidth to External Memory Total Warp IP Memory Traffic Peak Memory Bandwidth Approximation for Video Streams Peak Memory Bandwidth Approximation for Coefficient Streams Peak Memory Bandwidth Approximation for Cache Loads Memory Interface Bandwidth Requirements Example system sharing access to memory Multiple Warp IPs sharing access to memory
49.5. Warp IP Software API x
49.5.1. Using Warp IP Software 49.5.2. Warp IP Software Code Examples
50. White Balance Correction Intel® FPGA IP x
50.1. About the White Balance Correction IP 50.2. White Balance Correction IP Parameters 50.3. White Balance Correction IP Functional Description 50.4. White Balance Correction IP Registers 50.5. White Balance Correction IP Software API
50.1. About the White Balance Correction IP x
50.1.1. White Balance Correction IP Performance and Resources
50.3. White Balance Correction IP Functional Description x
50.3.1. White Balance Correction IP Interfaces
51. White Balance Statistics Intel® FPGA IP x
51.1. About the White Balance Statistics IP 51.2. White Balance Statistics IP Parameters 51.3. White Balance Statistics IP Interfaces 51.4. White Balance Statistics IP Registers 51.5. White Balance Statistics IP Software API
51.1. About the White Balance Statistics IP x
51.1.1. White Balance Statistics IP Performance and Resources
52. Design Security x
52.1. Memory Subsystems 52.2. Considering Design Security
1. About the Video and Vision Processing Suite
2. Getting Started with the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description
4. Video and Vision Processing IP Interfaces
5. Video and Vision Processing IP Registers
6. Video and Vision Processing IPs Software Programming Model
7. Protocol Converter Intel® FPGA IP
8. 1D LUT Intel® FPGA IP
9. 3D LUT Intel® FPGA IP
10. AXI-Stream Broadcaster Intel® FPGA IP
11. Bits per Color Sample Adapter Intel FPGA IP
12. Black Level Correction Intel® FPGA IP
13. Black Level Statistics Intel® FPGA IP
14. Chroma Key Intel® FPGA IP
15. Chroma Resampler Intel® FPGA IP
16. Clipper Intel® FPGA IP
17. Clocked Video Input Intel® FPGA IP
18. Clocked Video to Full-Raster Converter Intel® FPGA IP
19. Clocked Video Output Intel® FPGA IP
20. Color Space Converter Intel® FPGA IP
21. Defective Pixel Correction Intel® FPGA IP
22. Deinterlacer Intel® FPGA IP
23. Demosaic Intel® FPGA IP
24. FIR Filter Intel® FPGA IP
25. Frame Cleaner Intel® FPGA IP
26. Full-Raster to Clocked Video Converter Intel® FPGA IP
27. Full-Raster to Streaming Converter Intel® FPGA IP
28. Genlock Controller Intel® FPGA IP
29. Generic Crosspoint Intel® FPGA IP
30. Genlock Signal Router Intel® FPGA IP
31. Guard Bands Intel® FPGA IP
32. Histogram Statistics Intel® FPGA IP
33. Interlacer Intel® FPGA IP
34. Mixer Intel® FPGA IP
35. Pixels in Parallel Converter Intel® FPGA IP
36. Scaler Intel® FPGA IP
37. Stream Cleaner Intel® FPGA IP
38. Switch Intel® FPGA IP
39. Tone Mapping Operator Intel® FPGA IP
40. Test Pattern Generator Intel® FPGA IP
41. Unsharp Mask Intel® FPGA IP
42. Video and Vision Monitor Intel FPGA IP
43. Video Frame Buffer Intel® FPGA IP
44. Video Frame Reader Intel FPGA IP
45. Video Frame Writer Intel FPGA IP
46. Video Streaming FIFO Intel® FPGA IP
47. Video Timing Generator Intel® FPGA IP
48. Vignette Correction Intel® FPGA IP
49. Warp Intel® FPGA IP
50. White Balance Correction Intel® FPGA IP
51. White Balance Statistics Intel® FPGA IP
52. Design Security
53. Document Revision History for Video and Vision Processing Suite User Guide

49.3.4. External Memory for Warp IP

The IP requires access to two separate areas of external memory: one for its input and output video buffers and one for its coefficient tables. The processor system running the Warp Software API must be able to access the coefficient tables but does not need access to the buffer area.

Memory Space Allocation in External Memory

Table 954.   Warp IP Video Buffer Memory Region - maximum usageThe table defines how much space is required in external memory by the Warp IP for the video buffer region when you turn off Use easy warp and turn off Use single memory bounce. This space depends on the size of the images to be processed in a system. It is defined by the Memory frame buffer size parameter. Six buffers require space in total: four input and two output.
Buffer Space Configuration Region Size (MB) Memory Region Required Alignment (multiples of)
SD buffer size (1024x1024) 24 0x0180_0000 0x0200_0000
HD buffer size (2048x2048) 96 0x0600_0000 0x0800_0000
UHD buffer size (4096x4096) 384 0x1800_0000 0x2000_0000
Table 955.   Warp IP Video Buffer Memory Region - reduced usage

The table defines how much space is required in external memory by the Warp IP for the video buffer region when you turn on Use easy warp or turn on Use single memory bounce. This space depends on the size of the images to be processed in a system. It is defined by the Memory frame buffer size parameter. Four buffers require space in total.

Buffer Space Configuration Region Size (MB) Memory Region Required Alignment (multiples of)
SD buffer size (1024x1024) 16 0x0100_0000 0x0100_0000
HD buffer size (2048x2048) 64 0x0400_0000 0x0400_0000
UHD buffer size (4096x4096) 256 0x1000_0000 0x1000_0000

The IP passes the base address of the memory region allocated to the frame buffers to the software API using the ram_addr element in the structure.

The memory region that the coefficient tables require is related to the number of warp engines, the resolution of the images, and the type of warp. The IP only requires this memory region when you turn off Use easy warp.

Table 956.  Warp IP Coefficient Tables Memory RegionThe table shows the maximum size of the coefficient table memory region, per engine.
Warp Engines Region Size (MB) Memory Region Required Alignment (multiples of)
1 16 0x0100_0000 0x0100_0000
2 32 0x0200_0000 0x0200_0000

Bandwidth to External Memory

The performance of the interface from the Warp IP to the external memory is important for the correct operation of a system using the Warp IP.

The Warp IP generates a substantial amount of memory traffic. It has up to four video streams passing to and from external memory. In addition, each engine has three read streams to access the coefficient tables. All these streams combine to make Warp IP memory accesses complex. The streams affect how much efficiency you can obtain when accessing memory such as DDR4.

The Warp IP memory controller mitigates potential inefficiencies caused by these complex access patterns. It uses burst lengths of 8 beats for all its read and write accesses to improve the burst performance of DDR4 memory. It also attempts to cluster individual read and write bursts together to eliminate some of the issues with read and write turnaround dead time at the DDR4 interface.

These memory access patterns depend on the image transform that you apply. Some complex image transforms may reduce memory traffic because of the skip region functionality. When Use single memory bounce is off, one of the worst transforms for generated memory traffic is a unity warp that gives a 1:1 mapping between input and output pixels. When Use single memory bounce is on, memory traffic is proportional to the amount of compression in the vertical direction of the transform. The higher the amount of compression in the transform vertically, the higher the memory bandwidth.

The operation of the Warp IP is easier to predict when it is the only user of the DDR4 memory in a system. Ensure the Warp IP is the only high bandwidth user of the DDR4 memory in a system. When other high bandwidth accesses are made to the memory at the same time as the Warp IP, ensure that any interactions don’t adversely affect performance.

Total Warp IP Memory Traffic

Three different configurations of the warp IP affect the way it connects to the external memory and hence affect the total memory traffic:

  • When Use easy warp is on
  • Use easy warp is off and Use single memory bounce is either on or off.
Figure 123. External Memory Data Streams

The figure shows a schematic view of all the possible data streams the IP uses. Depending on the settings of Use easy warp and Use single memory bounce, the IP does not require all of these streams.

Table 957.  Active Data Streams for Different Configurations

The table shows which external memory data streams are active for the different configuration settings.

Data Stream Use easy warp on Use single memory bounce on Use single memory bounce off
Input video Active Active Active
Cache loads Active Active
Warped image Active
Coefficient reads Active Active
Output video Active Active

The bandwidth for each data stream is:

  • A video stream (input video, warped image and output video)
  • A coefficient stream (coefficient reads)
  • Cache loads (a scaled version of a video stream).

Peak Memory Bandwidth Approximation for Video Streams

The equation calculates the peak bandwidth (in bits per second) for the video streams passing through the warp (where number_of_lines includes blanking). Each pixel of data is transferred to or from external memory as a 32bit word.

Peak bandwidth = 32 * pixels_per_line * number_of_lines * frame_rate

Table 958.  Video Stream Memory Bandwidth Examples

The table shows the peak memory bandwidth per video stream for various resolutions and frame rates.

Resolution Frame Rate (fps) Peak Data Rate (Gbps)
3840x2160 (2250 lines) 60 16.6
3840x2160 (2250 lines) 30 8.3
1920x1080 (1125 lines) 60 4.2

Peak Memory Bandwidth Approximation for Coefficient Streams

You can approximate the memory bandwidth required by the coefficient streams as 9% of a video stream.

Table 959.  Coefficient Stream Memory Bandwidth Examples

The table shows the peak memory bandwidth per stream for various resolutions and frame rates.

Resolution Frame Rate (fps) Peak Data Rate (Gbps)
3840x2160 60 1.5
3840x2160 30 0.75
1920x1080 60 0.4

Peak Memory Bandwidth Approximation for Cache Loads

The memory bandwidth required by the IP for the cache loads is closely linked to the warp transform that the IP applies. The memory bandwidth is proportional to the bandwidth required by a standard video stream. It is also affected by Use single memory bounce.

When Use single memory bounce is off, the worst-case bandwidth required for cache loads is experienced for a 1:1 or unity warp and is approximately 25% higher than a normal video stream. The unity warp gives an upper bound for the bandwidth. Other transforms give lower.

When Use single memory bounce is on, the amount of vertical compression in the transform that the IP performs affects the bandwidth required for cache loads. A 1:1 or unity warp has a 1:1 vertical compression. The resultant cache load bandwidth is equivalent to the bandwidth for a standard video stream. In contrast, a 53 degree vertical keystone warp has a vertical compression approaching 2:1 in some regions. The maximum cache load bandwidth for this warp is two times the standard video stream bandwidth. The 2:1 ratio provides an upper bound for the cache load bandwidth for recommended operation.

The recommended 2:1 compression limit comes from the limitations of the low pass filtering that takes place in the bicubic pixel interpolation process when generating output pixels. However, you can generate transforms that have a compression ratio of greater than 2:1, which can potentially affect the single memory bounce memory bandwidth and reduce the final picture quality.

Memory Interface Bandwidth Requirements

Table 960.  Memory Interface Bandwidth Requirements – Easy WarpThe table shows the burst data rate scaling across resolutions and frame rates when Use easy warp is set to on. When Use easy warp is on, you can approximate the memory bandwidth using two video streams.
Resolution Frame Rate (fps) Maximum Burst Data Rate (Gbps)
3840x2160 60 34
3840x2160 30 17
1920x1080 60 8.5
Table 961.  Memory Interface Bandwidth Requirements – Single Memory BounceThe table shows the burst data rate scaling across resolutions and frame rates when Use single memory bounce is on. Tthe cache load data rate assumes a 2:1 vertical compression factor, which gives worst-case figures. When Use single memory bounce is on, you can approximate the memory bandwidth using one video stream, a coefficient stream, and the cache load stream (with an upper bound of twice the bandwidth of a standard video stream).
Resolution Frame Rate (fps) Maximum Burst Data Rate (Gbps)
3840x2160 60 51.3
3840x2160 30 25.7
1920x1080 60 8.5
Table 962.  Memory Interface Bandwidth Requirements - Double Memory Bounce The table shows the burst data rate scaling across resolutions and frame rates when Use single memory bounce is off. The cache load data rate assumes a 1:1 warp transform, which gives the worst-case figures. You can approximate the memory bandwidth using three video streams, a coefficient stream, and the cache load stream (with a 25% overhead above the bandwidth of a standard video stream).
Resolution Frame Rate (fps) Maximum Burst Data Rate (Gbps)
3840x2160 60 72
3840x2160 30 36
1920x1080 60 18

Intel references these burst data rates to the memory interface of the IP. The total data rates available are affected by other factors outside of the IP such as the performance of the interconnect fabric and the efficiency of the memory controller.

Example system sharing access to memory

In this example system the Warp IP shares the DDR4 interface with a frame buffer in a system that processes UHD frames at 60 fps. The system runs on an Intel Arria 10 GX Development Kit with the DDR4 EMIF running a 2,133 MHz interface to a DDR4 memory. This system has four memory-mapped hosts accessing the memory: processor, frame buffer read, frame buffer write, and warp.

Figure 124. Warp and Video Frame Buffer Platform DesignerThe figure shows the Platform Designer connectivity where the Frame Buffer II component is sharing access to the DDR4 EMIF with the Warp IP. The Frame Buffer is part of the same video processing pipeline as the Warp IP. For clarity, the figure only shows the Avalon memory-mapped Interfaces and Show Arbitration Shares is on.

For this system to work:

  • Configure Frame Buffer to use bursts of 32 beats for read and write.
  • Configure Frame Buffer to use read and write FIFO depths of 256
  • Set the arbitration weighting at the front end of the DDR4 EMIF to 16:1 in favor of the Warp IP (versus the processor and the Frame Buffer’s read and write interfaces connected through the mm_vfb_bridge component).
  • Set the Maximum pending read transactions parameter in the pipelined transfers section of the Avalon memory-mapped ports to be at 8.
  • Set Limit interconnect pipeline stages to for the domain at the front end of the DDR4 EMIF to 4. This limit helps to meet timing on the memory interface clock domain.

Memory accesses from the processor may adversely affect the performance of the rest of the system. If the performance is affected, increase the arbitration weightings at the mm_vfb_bridge component to be 1:2:2 or higher in favor of the Frame Buffer’s read and write interfaces. Alternatively, implement a fixed priority arbitration scheme at the mm_vfb_bridge to reduce the effect of the processor’s memory accesses.

Figure 125. Video Frame Buffer Parameterization
Figure 126. Maximum Pending Read Transactions
Figure 127. Parameterizing interconnect pipeline stages

Multiple Warp IPs sharing access to memory

Figure 128.  Multiple Warp IPs sharing access to memory The figure shows an example with two Warp IPs that share a DDR4 interface. To match the burst access patterns of the Warp IP, set the arbitration values at the combining interface to 8.
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