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Ixiasoft
1. About the Video and Vision Processing Suite
2. Getting Started with the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description
4. Video and Vision Processing IP Interfaces
5. Video and Vision Processing IP Registers
6. Video and Vision Processing IPs Software Programming Model
7. Protocol Converter Intel® FPGA IP
8. 3D LUT Intel® FPGA IP
9. Chroma Resampler Intel® FPGA IP
10. Clipper Intel® FPGA IP
11. Clocked Video to Full Raster Converter Intel® FPGA IP
12. Color Space Converter Intel® FPGA IP
13. Full Raster to Clocked Video Converter Intel FPGA IP
14. Full Raster to Streaming Converter Intel® FPGA IP
15. Guard Bands Intel® FPGA IP
16. Mixer Intel FPGA IP
17. Pixels in Parallel Converter IP
18. Scaler
19. Tone Mapping Operator Intel® FPGA IP
20. Test Pattern Generator Intel FPGA IP
21. Video Frame Buffer Intel FPGA IP
22. Video Streaming FIFO Intel FPGA IP
23. Warp Intel® FPGA IP
24. Document Revision History for Video and Vision Processing Suite User Guide
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Ixiasoft
22.3. Video Streaming FIFO IP Interfaces
Name | Direction | Width | Description |
---|---|---|---|
Clocks and resets | |||
main_clock_clk | In | 1 | AXI4-S processing clock. Only when you turn off Dual clock. |
main_reset_rst | In | 1 | AXI4-S processing reset. Only when you turn off Dual clock |
in_clock_clk | In | 1 | AXI4-S processing clock for the input interface domain. Only when you turn on Dual clock. |
in_reset_rst | In | 1 | AXI4-S processing reset for the input interface domain. Only when you turn on Dual clock. |
out_clock_clk | In | 1 | AXI4-S processing clock for the output interface domain. Only when you turn on Dual clock. |
out_reset_rst | In | 1 | AXI4-S processing reset for the output interface domain. Only when you turn on Dual clock. |
Intel FPGA streaming video interfaces |
|||
Port name | Direction | Width | Description |
axi4s_vid_in_tdata | In | AXI4S data in. | |
axi4s_vid_in_tvalid | In | 1 | AXI4-S data valid. |
axi4s_vid_in_tuser | In | AXI4-S tuser tuser[0] indicates start of video frame when asserted tuser[1] indicates the start of a non-video packet when asserted. |
|
axi4s_vid_in_tlast | In | 1 | AXI4-S end of packet. |
axi4s_vid_in_tready | Out | 1 | AXI4-S data ready. |
axi4s_vid_out_tdata | Out | 51 | AXI4-S data in. |
axi4s_vid_out_tvalid | Out | 1 | AXI4-S data valid. |
axi4s_vid_in_tuser | Out | 52 | AXI4-S tuser tuser[0] indicates start of video frame when asserted tuser[1] indicates the start of a non-video packet when asserted. |
axi4s_vid_out_tlast | Out | 1 | AXI4-S end of packet. |
axi4s_vid_out_tready | In | 1 | AXI4-S data ready. |
Related Information
51
The equation gives all tdata widths in these interfaces:
max (ceil((bits per color sample x number of color planes x pixels in parallel) / 8) x 8, 16)