Video and Vision Processing Suite Intel® FPGA IP User Guide

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Date 2/15/2022
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Document Table of Contents
Document Table of Contents x
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. Chroma Resampler Intel® FPGA IP 10. Clipper Intel® FPGA IP 11. Clocked Video to Full Raster Converter Intel® FPGA IP 12. Color Space Converter Intel® FPGA IP 13. Full Raster to Clocked Video Converter Intel FPGA IP 14. Full Raster to Streaming Converter Intel® FPGA IP 15. Guard Bands Intel® FPGA IP 16. Mixer Intel FPGA IP 17. Pixels in Parallel Converter IP 18. Scaler 19. Tone Mapping Operator Intel® FPGA IP 20. Test Pattern Generator Intel FPGA IP 21. Video Frame Buffer Intel FPGA IP 22. Video Streaming FIFO Intel FPGA IP 23. Warp Intel® FPGA IP 24. Document Revision History for Video and Vision Processing Suite User Guide
1. About the Video and Vision Processing Suite x
1.1. Device Family Support 1.2. Video and Vision Processing IPs Release Information 1.3. Video and Vision Processing IPs Features 1.4. Lite versus Full IP Variants 1.5. Glossary of Video and Vision Terminology
2. Getting Started with the Video and Vision Processing IPs x
2.1. Video and Vision Processing IP Time-out Behavior 2.2. Generating a Video and Vision Processing IP 2.3. Simulating the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description x
3.1. Auxiliary Control Packets 3.2. Latency 3.3. IP Debugging Features 3.4. Stall Behavior and Error Recovery 3.5. Avalon Streaming Video Protocol Versus Intel FPGA Streaming Video Protocol
5. Video and Vision Processing IP Registers x
5.1. Video and Vision Processing IP Control Examples
7. Protocol Converter Intel® FPGA IP x
7.1. About the Protocol Converter IP 7.2. Protocol Converter IP Parameters 7.3. Protocol Converter IP Functional Description 7.4. Protocol Converter IP Interfaces 7.5. Protocol Converter IP Registers 7.6. Protocol Converter IP Software API
7.1. About the Protocol Converter IP x
7.1.1. Protocol Converter IP Performance and Resources
8. 3D LUT Intel® FPGA IP x
8.1. About the 3D LUT Intel® FPGA IP 8.2. 3D LUT IP Parameters 8.3. 3D LUT IP Block Description 8.4. 3D LUT IP Registers 8.5. 3D LUT IP Software API
8.1. About the 3D LUT Intel® FPGA IP x
8.1.1. 3D LUT IP Features 8.1.2. 3D LUT IP Performance IP and Resource Information
8.3. 3D LUT IP Block Description x
8.3.1. 3D LUT IP Interfaces 8.3.2. 3D LUT IP Latency
9. Chroma Resampler Intel® FPGA IP x
9.1. About the Chroma Resampler IP 9.2. Chroma Resampler IP Parameters 9.3. Chroma Resampler IP Functional Description 9.4. Chroma Resampler IP Registers 9.5. Chroma Resampler IP Software API
9.1. About the Chroma Resampler IP x
9.1.1. Chroma Resampler Performance and Resources
9.3. Chroma Resampler IP Functional Description x
9.3.1. Chroma Resampler IP Interfaces
10. Clipper Intel® FPGA IP x
10.1. About the Clipper IP 10.2. Clipper IP Parameters 10.3. Clipper IP Interfaces 10.4. Clipper IP Registers 10.5. Clipper IP Software API
10.1. About the Clipper IP x
10.1.1. Clipper IP Performance and Resources
11. Clocked Video to Full Raster Converter Intel® FPGA IP x
11.1. About the Clocked Video to Full Raster Converter IP 11.2. Clocked Video to Full Raster Converter Parameters 11.3. Clocked Video to Full Raster Converter Block Description 11.4. Clocked Video Converter to Full Raster IP Registers
11.1. About the Clocked Video to Full Raster Converter IP x
11.1.1. Clocked Video to Full Raster Converter Features 11.1.2. Clocked Video to Full Raster Converter Performance and Resources
11.3. Clocked Video to Full Raster Converter Block Description x
11.3.1. Clocked Video to Full Raster Converter Interfaces
12. Color Space Converter Intel® FPGA IP x
12.1. About the Color Space Converter IP 12.2. Color Space Converter IP Parameters 12.3. Color Space Converter IP Functional Description 12.4. Color Space Converter IP Registers 12.5. Color Space Converter IP Software API
12.1. About the Color Space Converter IP x
12.1.1. Color Space Converter IP Features 12.1.2. Color Space Converter IP Performance and Resources
12.3. Color Space Converter IP Functional Description x
12.3.1. Color Space Converter IP Interfaces
13. Full Raster to Clocked Video Converter Intel FPGA IP x
13.1. About the Full Raster to Clocked Video Converter 13.2. Full Raster to Clocked Video Converter Parameters 13.3. Full Raster to Clocked Video Converter Block Description 13.4. Full Raster to Clocked Video Converter Registers
13.1. About the Full Raster to Clocked Video Converter x
13.1.1. Full Raster to Clocked Video Converter Features 13.1.2. Full Raster to Clocked Video Converter Performance and Resource Utilization
13.3. Full Raster to Clocked Video Converter Block Description x
13.3.1. Full Raster to Clocked Video Converter Interfaces
14. Full Raster to Streaming Converter Intel® FPGA IP x
14.1. About the Full Raster to Streaming Converter IP 14.2. Full Raster to Streaming Converter Parameters 14.3. Full Raster to Streaming Converter Block Description
14.1. About the Full Raster to Streaming Converter IP x
14.1.1. Full Raster to Streaming Converter Features 14.1.2. Full Raster to Streaming Converter Performance and Resources
14.3. Full Raster to Streaming Converter Block Description x
14.3.1. Full Raster to Streaming Converter Interfaces
15. Guard Bands Intel® FPGA IP x
15.1. About the Guard Bands IP 15.2. Guard Bands IP Parameters 15.3. Guard Bands IP Interfaces 15.4. Guard Bands IP Registers 15.5. Guard Bands IP Software API
15.1. About the Guard Bands IP x
15.1.1. Guard Bands IP Performance and Resources
16. Mixer Intel FPGA IP x
16.1. About the Mixer IP 16.2. Mixer IP Parameters 16.3. Mixer IP Functional Description 16.4. Mixer IP Registers 16.5. Mixer IP Software API
16.1. About the Mixer IP x
16.1.1. Mixer IP Performance and Resources
16.3. Mixer IP Functional Description x
16.3.1. Mixer IP Interfaces
17. Pixels in Parallel Converter IP x
17.1. About the Pixels in Parallel Converter IP 17.2. Pixels in Parallel IP Converter Parameters 17.3. Pixels in Parallel Converter Interfaces 17.4. Pixels in Parallel Converter Registers 17.5. Pixels in Parallel Converter IP Software API
17.1. About the Pixels in Parallel Converter IP x
17.1.1. Pixels in Parallel IP Converter Performance and Resources
18. Scaler x
18.1. About the Scaler 18.2. Scaler IP Parameters 18.3. Scaler IP Functional Description 18.4. Scaler IP Registers 18.5. Scaler IP Software API
18.1. About the Scaler x
18.1.1. Scaler IP Performance and Resources
18.2. Scaler IP Parameters x
18.2.1. Updating Scaler IP Runtime Coefficients
18.3. Scaler IP Functional Description x
18.3.1. Scaler IP Interfaces
19. Tone Mapping Operator Intel® FPGA IP x
19.1. About the Tone Mapping Operator IP 19.2. TMO IP Parameters 19.3. TMO IP Block Description 19.4. TMO IP Registers 19.5. TMO IP Software API
19.1. About the Tone Mapping Operator IP x
19.1.1. TMO IP Features 19.1.2. TMO IP Performance and Resource Utilization
19.3. TMO IP Block Description x
19.3.1. TMO IP Interfaces 19.3.2. TMO IP Latency
20. Test Pattern Generator Intel FPGA IP x
20.1. About the Test Pattern Generator IP 20.2. Test Pattern Generator IP Parameters 20.3. Test Pattern Generator IP Functional Description 20.4. Test Pattern Generator IP Registers 20.5. Test Pattern Generator IP Software API
20.1. About the Test Pattern Generator IP x
20.1.1. Test Pattern Generator IP Performance and Resources
20.3. Test Pattern Generator IP Functional Description x
20.3.1. Test Pattern Generator IP Interfaces
21. Video Frame Buffer Intel FPGA IP x
21.1. About the Video Frame Buffer IP 21.2. Video Frame Buffer IP Parameters 21.3. Video Frame Buffer IP Functional Description 21.4. Video Frame Buffer IP Registers 21.5. Video Frame Buffer IP Software API
21.1. About the Video Frame Buffer IP x
21.1.1. Video Frame Buffer Performance and Resources
21.3. Video Frame Buffer IP Functional Description x
21.3.1. Video Frame Buffer IP Interfaces
22. Video Streaming FIFO Intel FPGA IP x
22.1. About the Video Streaming FIFO IP 22.2. Video Streaming FIFO IP Parameters 22.3. Video Streaming FIFO IP Interfaces
22.1. About the Video Streaming FIFO IP x
22.1.1. Video Streaming FIFO IP Performance and Resources
23. Warp Intel® FPGA IP x
23.1. About the Warp IP 23.2. Warp IP Parameters 23.3. Warp IP Block Description 23.4. Warp IP Registers 23.5. Warp IP Software API
23.1. About the Warp IP x
23.1.1. Warp IP Features 23.1.2. Warp IP Performance and Resource Utilization
23.3. Warp IP Block Description x
23.3.1. Warp IP Interfaces 23.3.2. Warp IP Latency 23.3.3. External Memory for Warp IP
23.5. Warp IP Software API x
23.5.1. Using Warp IP Software 23.5.2. Warp IP Software Code Examples
1. About the Video and Vision Processing Suite
2. Getting Started with the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description
4. Video and Vision Processing IP Interfaces
5. Video and Vision Processing IP Registers
6. Video and Vision Processing IPs Software Programming Model
7. Protocol Converter Intel® FPGA IP
8. 3D LUT Intel® FPGA IP
9. Chroma Resampler Intel® FPGA IP
10. Clipper Intel® FPGA IP
11. Clocked Video to Full Raster Converter Intel® FPGA IP
12. Color Space Converter Intel® FPGA IP
13. Full Raster to Clocked Video Converter Intel FPGA IP
14. Full Raster to Streaming Converter Intel® FPGA IP
15. Guard Bands Intel® FPGA IP
16. Mixer Intel FPGA IP
17. Pixels in Parallel Converter IP
18. Scaler
19. Tone Mapping Operator Intel® FPGA IP
20. Test Pattern Generator Intel FPGA IP
21. Video Frame Buffer Intel FPGA IP
22. Video Streaming FIFO Intel FPGA IP
23. Warp Intel® FPGA IP
24. Document Revision History for Video and Vision Processing Suite User Guide

15.4. Guard Bands IP Registers

Each register is either read-only (RO) or read-write (RW).
Table 166.  Guard Bands IP RegistersIn the software API the register names appear with a prefix of INTEL_VVP, INTEL_VVP_CORE or INTEL_VVP_GUARD_BANDS as appropriate and with an optional REG suffix
Address Register Access Description
Lite37 Full
Parameterization registers
0x0000 VID_PID RO RO

Read this register to retrieve the Guard Bands Intel FPGA IP product ID.

This register always returns 0x6AF7_0231.
0x0004 VERSION RO RO

Read this register to retrieve the version information for the Intel Quartus Prime release that Intel uses to build the Configurable Guard Bands IP.

0x0008 LITE_MODE RO RO

Read this register to determine if Lite mode is on or off.

This register returns 0 when you turn off Lite mode and 1 for when you turn on Lite mode.

0x000C DEBUG_ENABLED RO RO

Read this register to determine if Debug features is on or off.

0x0010 NUM_GB_VALUES RO RO Read this register to determine the number of guard bands that you can set. Equivalent to number of color planes or (number of color planes + 1) if you turn on 4:2:2 support.
0x0014 to 0x011F - - - Unused.

Control and debug registers

For more information, refer to Control Packets

0x0120 IMG_INFO_WIDTH RW RO When you turn on Lite, the expected width of the incoming video fields. When you turn off Lite, the received width in image information packets.
0x0124 IMG_INFO_HEIGHT RW RO When you turn on Lite, the expected height of the incoming video fields. When you turn off Lite, the received height in image information packets.
0x0128 IMG_INFO_INTERLACE RW RO When you turn on Lite, the expected interlace information of the incoming video fields. When you turn off Lite, the received interlace information in image information packets.
0x012C Reserved RW RO Unused.
0x0130 IMG_INFO_COLORSPACE RW RO When you turn on Lite, the expected color space of the incoming video fields. When you turn off Lite, the received color space in image information packets.
0x0134 IMG_INFO_SUBSAMPLING RW RO When you turn on Lite, the expected chroma sub-sampling of the incoming video fields. When you turn off Lite, the received chroma sub-sampling in image information packets.
0x0138 IMG_INFO_COSITING RW RO When you turn on Lite, the expected chroma co-siting of the incoming video fields. When you turn off Lite, the received chroma co-siting in image information packets.
0x013C IMG_INFO_FIELD_COUNT RO RO The received field count field in image information packets.
0x0140 STATUS RO RO

Bit 0: Status bit.

1 means the IP is processing a video field, 0 otherwise.

When you turn off Lite:

Bit 1: Pending register updates bit.

Any writes to the specification registers (0x0148 - 0x0154) cause the IP to raise the pending register updates bit, to indicate outstanding changes to the guard band settings.

The IP lowers this bit at the start of the first packet for a new frame (first packet after the EOP) after a write to the COMMIT register.

0x0144 COMMIT RW RW

The IP uses this register with the STATUS register Pending register updates bit.

Write any value to this register after writing new values to any of the specification registers (0x0148 - 0x0154). The configurable guard bands change to the new guard band specification values at the start of the next video frame after the IP writes to this register.

The COMMIT register ensures atomic register updates, avoiding the IP only applying some of the updated register values for the next incoming frame.

Specification registers
0x0148 GB_0_VALUES RW RW

Write to this register to set the lower and upper guard band values for color plane 0.
0x014C GB_1_VALUES RW RW

Write to this register to set the lower and upper guard band values for color plane 1. Unused if NUM_GB_VALUES < 2.

0x0150 GB_2_VALUES RW RW

Write to this register to set the lower and upper guard band values for color plane 2.

Unused if NUM_GB_VALUES < 3.

0x0154 GB_3_VALUES RW RW

Write to this register to set the lower and upper guard band values for color plane 3.

Unused if NUM_GB_VALUES < 4.

Register Bit Descriptions

Table 167.  VID_PID
Name Bits Description
Guard Bands Intel FPGA IP vendor ID and product ID 31:0 This register always returns 0x6AF7_0231.
  • 15:0 is the product ID and always returns 0x0231
  • 31:16 is the vendor ID and always returns 0x6AF7
Table 168.  VERSION
Name Bits Description
Register map version 7:0 Register map version. Returns 0x01.
QPDS patch revision 15:8 Returns 0x00
QPDS update revision 23:16 Updated for each release. For 21.4, returns 0x04
QPDS major revision 31:24 Updated for each release. For 21.4, returns 0x15.
Table 169.  LITE_MODE
Name Bits Description
Lite mode parameterization bit 0 Returns 1 if you turn on lite mode.
Unused 31:1 Unused.
Table 170.  DEBUG_ENABLED
Name Bits Description
Debug features parameterization bit 0 Returns 1 if you turn on debug features.
Unused 31:1 Unused.
Table 171.  NUM_GB_VALUES
Name Bits Description
Number of GB values used 3:0 This field indicates number of guard bands that are active. Equivalent to number of color planes or (number of color planes + 1) if you turn on 4:2:2 support.
Unused 31:4 Unused.
Table 172.  IMG_INFO_WIDTH
Name Bits Description
Width bits 15:0

When you turn on Lite, write to this register to set the expected width of the incoming video fields.

When you turn off Lite and turn on Debug features, this register returns the width field from the most recently received.

Unused 31:16 Unused.
Table 173.  IMG_INFO_HEIGHT
Name Bits Description
Height bits 15:0

When you turn on Lite, write to this register to set the expected height of the incoming video fields.

When you turn off Lite and turn on Debug features, this register returns the height field from the most recently received.

Unused 31:16 Unused.
Table 174.  IMG_INFO_INTERLACE
Name Bits Description
interlaced bits 3:0

When you turn on Lite, write to this register to set the expected interlacing of the incoming video fields.

When you turn off Lite and turn on Debug features, this register returns the intlaceNibble field from the most recently received image information packet .

Unused 31:4 Unused.
Table 175.  IMG_INFO_COLORSPACE
Name Bits Description
Color space code bits 6:0

When you turn on Lite, write to this register to set the expected color space of the incoming video fields.

When you turn off Lite and turn on Debug features, this register returns the CSP field from the most recently received image information packet .

Unused 31:7 Unused.
Table 176.  IMG_INFO_SUBSAMPLING
Name Bits Description
Subsampling code bits 1:0

When you turn on Lite, write to this register to set the expected chroma sub-sampling of the incoming video fields.

When you turn off Lite and turn on Debug features, this register returns the SUBSA field from the most recently received image information packet.

Unused 31:2 Unused.
Table 177.  IMG_INFO_COSITING
Name Bits Description
Cosite code bits 1:0

When you turn on Lite, write to this register to set the expected chroma co-siting of the incoming video fields.

When you turn off Lite and turn on Debug features, this register returns the COSITE field from the most recently received image information packet.

Unused 31:2 Unused.
Table 178.  STATUS
Name Bits Description
Status bit 0 1 means configurable guard bands are processing a video field, 0 otherwise.
Pending register updates bit 1 1 means configurable guard bands have pending updates, 0 otherwise.
Table 179.  COMMIT
Name Bits Description
Commit bits 31:0 Write to any bits to trigger a commit.
Table 180.  GB_0_VALUES
Name Bits Description
GB_0_LOWER_VALUE 15:0 Write to this register to set the lower guard band value for color plane 0.
GB_0_UPPER_VALUE 31:16 Write to this register to set the upper guard band value for color plane 0.
Table 181.  GB_1_VALUES
Name Bits Description
GB_1_LOWER_VALUE 15:0 Write to this register to set the lower guard band value for color plane 1. Unused if NUM_GB_VALUES < 2.
GB_1_UPPER_VALUE 31:16 Write to this register to set the upper guard band value for color plane 1. Unused if NUM_GB_VALUES < 2.
Table 182.   GB_2_VALUES
Name Bits Description
GB_2_LOWER_VALUE 15:0 Write to this register to set the lower guard band value for color plane 2. Unused if NUM_GB_VALUES < 3.
GB_2_UPPER_VALUE 31:16 Write to this register to set the upper guard band value for color plane 2. Unused if NUM_GB_VALUES < 3.
Table 183.  GB_3_VALUES
Name Bits Description
GB_3_LOWER_VALUE 15:0 Write to this register to set the lower guard band value for color plane 3. Unused if NUM_GB_VALUES < 4.
GB_3_UPPER_VALUE 31:16 Write to this register to set the upper guard band value for color plane 3. Unused if NUM_GB_VALUES < 4.
37

When you turn on lite mode, registers are RW only if you turn on Debug features, otherwise they are WO. For full, turn off lite mode.

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