Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 2/15/2022
Public

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17.4. Pixels in Parallel Converter Registers

Each register is either read-only (RO) or read-write (RW). Writes to RO registers complete but the IP ignores them. A read to any RW register also completes, but returns undefined data by default. These registers are RW to save FPGA resources. To enable readback of the values you write to these registers, you must turn on Debug features when you configure the IP.
Table 218.  Pixels in Parallel IP RegistersIn the software API the register names appear with a prefix of INTEL_VVP, INTEL_VVP_CORE or INTEL_VVP_CLIPPER as appropriate and with an optional REG suffix
Address Register Access Description
Parameterization registers
0x0000 VID_PID RO

Read this register to retrieve the pixels in parallel converter product ID.

This register always returns 0x6AF7_0239.

0x0004 VERSION RO

Read this register to retrieve the version information for the Intel Quartus release that Intel uses to build the pixels in parallel converter.

0x0008 LITE_MODE RO

Read this register to determine if Lite mode is on.

This register always returns 1 as the Avalon memory-mapped control interface is only available when you turn on Lite mode.

0x000C DEBUG_ENABLED RO

Read this register to determine if Debug features is on.

This register returns 1 if reads to other registers designated as RW return the last value the IP writes to the register, or an undefined value.

0x0010 to 0x011F - - Unused
Control and debug registers

For more information, refer to Control Packets

0x0120 IMG_INFO_WIDTH RW Set the expected width of incoming video fields.
0x0124 to 0x0130 - - Unused.
0x0134 IMG_INFO_SUBSAMPLING RW The expected chroma subsampling of the incoming video fields.
0x0138 to 0x013C - - Unused.
0x0140 STATUS RO

Bit 0: Status bit.

1 means the pixels in parallel converter is processing a video field, 0 otherwise.

Register Bit Descriptions

Table 219.  VID_PID
Name Bits Description
Pixels in parallel converter version ID and product ID 31:0 This register always returns 0x6AF7_0239.
  • 15:0 is the product ID and always returns 0x0239
  • 31:16 is the vendor ID and always returns 0x6AF7
Table 220.  VERSION
Name Bits Description
Lite mode parameterization bit 7:0 Register map version. Returns 0x01.
QPDS patch revision 15:8 Returns 0x00.
QPDS update revision 23:16 Updated for each release. For 21.4 this returns 0x04.
QPDS major revision 31:24 Updated for each release. For 21.4 this returns 0x15.
Table 221.   LITE_MODE
Name Bits Description
Lite mode parameterization bit 0 Returns 1 if you turn on Lite mode.
Unused 31:1 Unused.
Table 222.  DEBUG_ENABLED
Name Bits Description
Debug features parameterization bit 0 Returns 1 if you turn on Debug features.
Unused 31:1 Unused.
Table 223.  IMG_INFO_WIDTH
Name Bits Description
Width bits 15:0 Write to this register to set the expected width of the incoming video fields.
unused 31:16 Unused.
Table 224.  IMG_INFO_SUBSAMPLING
Name Bits Description
SubSa code bits 1:0 Write to this register to set the expected chroma sub-sampling of the incoming video fields.
unused 31:2 Unused.
Table 225.  STATUS
Name Bits Description
Status bit 0 1 means the pixels in parallel converter is processing a video field, 0 otherwise.
unused 31:1 Unused.