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Ixiasoft
1. About the Video and Vision Processing Suite
2. Getting Started with the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description
4. Video and Vision Processing IP Interfaces
5. Video and Vision Processing IP Registers
6. Video and Vision Processing IPs Software Programming Model
7. Protocol Converter Intel® FPGA IP
8. 3D LUT Intel® FPGA IP
9. Chroma Resampler Intel® FPGA IP
10. Clipper Intel® FPGA IP
11. Clocked Video to Full Raster Converter Intel® FPGA IP
12. Color Space Converter Intel® FPGA IP
13. Full Raster to Clocked Video Converter Intel FPGA IP
14. Full Raster to Streaming Converter Intel® FPGA IP
15. Guard Bands Intel® FPGA IP
16. Mixer Intel FPGA IP
17. Pixels in Parallel Converter IP
18. Scaler
19. Tone Mapping Operator Intel® FPGA IP
20. Test Pattern Generator Intel FPGA IP
21. Video Frame Buffer Intel FPGA IP
22. Video Streaming FIFO Intel FPGA IP
23. Warp Intel® FPGA IP
24. Document Revision History for Video and Vision Processing Suite User Guide
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Ixiasoft
10.3. Clipper IP Interfaces
Name | Direction | Width | Description |
---|---|---|---|
Clocks and resets | |||
main_clock_clk | In | 1 | AXI4-S processing clock. |
main_reset_rst | In | 1 | AXI4-S processing reset. |
agent_clock_clk | In | 1 | Optional agent interface clock. |
agent_reset_rst | In | 1 | Optional agent interface reset. |
Control interfaces | |||
av_mm_control_agent_address | In | 7 | Avalon memory-mapped agent address |
av_mm_control_agent_write | In | 1 | Avalon memory-mapped agent write. |
av_mm_control_agent_writedata | In | 32 | Avalon memory-mapped agent write data. |
av_mm_control_agent_byteenable | In | 4 | Avalon memory-mapped agent byte enable. |
av_mm_control_agent_read | In | 1 | Avalon memory-mapped agent read. |
av_mm_control_agent_readdata | Out | 32 | Avalon memory-mapped agent read data. |
av_mm_control_agent_readdatavalid | Out | 1 | Avalon memory-mapped agent read. |
av_mm_control_agent_waitrequest | Out | 1 | Avalon memory-mapped agent wait request. |
Intel FPGA streaming video interfaces | |||
axi4s_vid_in_tdata | In | AXI4-S data in. | |
axi4s_vid_in_tvalid | In | 1 | AXI4-S data valid. |
axi4s_vid_in_tuser[0] | In | 1 | AXI4-S start of video frame. |
axi4s_vid_in_tuser[1] | In | 1 | AXI4-S control or data packet. |
axi4s_vid_in_tuser[N-1:2] | In | Unused. | |
axi4s_vid_in_tlast | In | 1 | AXI4-S end of packet. |
axi4s_vid_in_tready | Out | 1 | AXI4-S data ready. |
axi4s_vid_out_tdata | Out | 11 | AXI4-S data out. |
axi4s_vid_out_tvalid | Out | 1 | AXI4-S data valid. |
axi4s_vid_out_tuser[0] | Out | 1 | AXI4-S start of video frame. |
axi4s_vid_out_tuser[1] | Out | 1 | AXI4-S control or data packet. |
axi4s_vid_out_tuser[N-1:2] | Out | 12 | Unused. |
axi4s_vid_out_tlast | Out | 1 | AXI4-S end of packet. |
axi4s_vid_out_tready | In | 1 | AXI4-S data ready. |
Related Information
11 The equation gives all tdata widths sizes in these interfaces:
max (floor(((bits per color sample x number of color planes x pixels in parallel) + 7) / 8) x 8, 16)
12 This equation gives all tuser widths sizes in these interfaces N = ceil (tdata width / 8)