Intel® Quartus® Prime Pro Edition Settings File Reference Manual

ID 683296
Date 12/12/2022
Public

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Document Table of Contents

SIM_TAP_REGISTER_D_Q_PORTS

Adds the D and Q ports of a register node to the list of signals for which output waveforms are shown in the simulation report. This option makes the D and Q ports of a register node observable during Functional Simulation.

Type

Boolean

Device Support

  • This setting can be used in projects targeting any Intel FPGA device family.

Syntax


set_instance_assignment -name SIM_TAP_REGISTER_D_Q_PORTS -to <to> -entity <entity name> <value>