Intel® Quartus® Prime Pro Edition Settings File Reference Manual

ID 683296
Date 12/12/2022
Public

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Document Table of Contents

BLOCK_DESIGN_NAMING

Specify the naming scheme used for the block design. This option is ignored if it is assigned to anything other than a design entity.

Type

Enumeration

Values

  • Auto
  • MaxPlusII
  • QuartusII

Device Support

  • This setting can be used in projects targeting any Intel FPGA device family.

Notes

This assignment is included in the Analysis & Synthesis report.

This assignment supports synthesis wildcards.

Syntax


set_global_assignment -name BLOCK_DESIGN_NAMING -entity <entity name> <value>
set_instance_assignment -name BLOCK_DESIGN_NAMING -to <to> -entity <entity name> <value>
set_global_assignment -name BLOCK_DESIGN_NAMING <value>

Default Value

Auto

Example


set_global_assignment -name block_design_naming MaxPlusII
set_instance_assignment -name block_design_naming MaxPlusII -to top