Intel® Quartus® Prime Pro Edition Settings File Reference Manual

ID 683296
Date 12/12/2022
Public

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ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS

Directs the Timing Analyzer to analyze latches as synchronous elements, rather than as combinational elements. Although latches continue to be implemented as a LUT feeding back onto itself, turning on this option directs the Timing Analyzer to analyze all latches as synchronous elements. Specifically, the clock enable is analyzed as an inverted clock. The Timing Analyzer reports the results of setup and hold analysis on these latches

Type

Boolean

Device Support

  • This setting can be used in projects targeting any Intel FPGA device family.

Notes

None

Syntax


set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS <value>

Default Value

On