Intel® Quartus® Prime Pro Edition Settings File Reference Manual

ID 683296
Date 12/12/2022
Public

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Document Table of Contents

VIRTUAL_PIN

Specifies whether an I/O element in a lower-level design entity can be temporarily mapped to a logic element and not to a pin during compilation. The virtual pin is then implemented as a LUT. This option should be specified only for I/O elements that become nodes when imported to the top-level design.

Type

Boolean

Device Support

  • Agilex 7
  • Intel® Arria® 10
  • Intel® Cyclone® 10 GX
  • Intel® Stratix® 10

Notes

This assignment supports synthesis wildcards.

Syntax


set_instance_assignment -name VIRTUAL_PIN -to <to> -entity <entity name> <value>