Enhanced Configuration (EPC) Devices Datasheet

Download PDF
ID 683253
Date 5/04/2016
Public
Document Table of Contents
Document Table of Contents x
1. Enhanced Configuration (EPC) Devices Datasheet
1. Enhanced Configuration (EPC) Devices Datasheet x
1.1. Supported Devices 1.2. Features 1.3. Functional Description 1.4. Pin Description 1.5. Power-On Reset 1.6. Power Sequencing 1.7. Programming and Configuration File Support 1.8. IEEE Std. 1149.1 (JTAG) Boundary-Scan 1.9. Timing Information 1.10. Operating Conditions 1.11. Package 1.12. Document Revision History
1.3. Functional Description x
1.3.1. FPGA Configuration 1.3.2. External Flash Interface 1.3.3. Intel Flash-Based EPC Device Protection 1.3.4. Dynamic Configuration (Page Mode) 1.3.5. Real-Time Decompression 1.3.6. Programmable Configuration Clock 1.3.7. Flash In-System Programming (ISP)
1.3.1. FPGA Configuration x
1.3.1.1. Configuration Signals 1.3.1.2. Fast Passive Parallel Configuration 1.3.1.3. Passive Serial Configuration 1.3.1.4. Concurrent Configuration
1.3.7. Flash In-System Programming (ISP) x
1.3.7.1. JTAG-based Programming 1.3.7.2. Programming using External Flash Interface
1.11. Package x
1.11.1. Package Layout Recommendation
1. Enhanced Configuration (EPC) Devices Datasheet

1.9. Timing Information

Figure 7. Configuration Timing Waveform Using an EPC Device
Table 13.   EPC Device Configuration Timing Parameters
Symbol Parameter Condition Min Typ Max Unit
fDCLK DCLK frequency 40% duty cycle — — 66.7 MHz
tDCLK DCLK period — 15 — — ns
tHC DCLK duty cycle high time 40% duty cycle 6 — — ns
tLC DCLK duty cycle low time 40% duty cycle 6 — — ns
tCE OE to first DCLK delay — 40 — — ns
tOE OE to first DATA available — 40 — — ns
tOH DCLK rising edge to DATA change — 6 — — ns
tCF 7 OE assert to DCLK disable delay — 277 — — ns
tDF 7 OE assert to DATA disable delay — 277 — — ns
tRE 8 DCLK rising edge to OE — 60 — — ns
tLOE OE assert time to assure reset — 60 — — ns
fECLK 9 EXCLK input frequency 40% duty cycle — — 100 MHz
6 To calculate tOH, use the following equation: tOH = 0.5 (DCLK period) - 2.5 ns.
7 This parameter is used for CRC error detection by the FPGA.
8 This parameter is used for CONF_DONE error detection by the EPC device.
9 The FPGA VCCINT ramp time should be less than 1ms for 2-ms POR and it should be less than 70 ms for 100-ms POR.
Level Two Title