1.4. Pin Description
The following tables list the EPC device pins. These tables include configuration interface pins, external flash interface pins, JTAG interface pins, and other pins.
| Pin Name | Pin Type | Description |
|---|---|---|
| DATA [7..0] | Output | Configuration data output bus. DATA changes on each falling edge of DCLK. DATA is latched into the FPGA on the rising edge of DCLK. |
| DCLK | Output | The DCLK output pin from the EPC device serves as the FPGA configuration clock. DATA is latched by the FPGA on the rising edge of DCLK. |
| nCS | Input | The nCS pin is an input to the EPC device and is connected to the FPGA’s CONF_DONE signal for error detection after all configuration data is transmitted to the FPGA. The FPGA will always drive nCS and OE low when nCONFIG is asserted. This pin contains a programmable internal weak pull-up resistor of 6 KW that can be disabled or enabled in the Quartus II software through the Disable nCS and OE pull-ups on configuration device option. |
| nINIT_CONF | Open-Drain Output | The nINIT_CONF pin can be connected to the nCONFIG pin on the FPGA to initiate configuration from the EPC device using a private JTAG instruction. This pin contains an internal weak pull-up resistor of 6K W that is always active. The INIT_CONF pin does not need to be connected if its functionality is not used. If nINIT_CONF is not used, nCONFIG must be pulled to VCC either directly or through a pull-up resistor. |
| OE | Open-Drain Bidirectional | This pin is driven low when POR is not complete. A user-selectable 2-ms or This pin is driven low when POR is not complete. A user-selectable 2-ms or 100-ms counter holds off the release of OE during initial power up to permit voltage levels to stabilize. POR time can be extended by externally holding OE low. OE is connected to the FPGA nSTATUS signal. After the EPC device controller releases OE, it waits for the nSTATUS-OE line to go high before starting the FPGA configuration process. This pin contains a programmable internal weak pull-up resistor of 6 KW that can be disabled or enabled in the Quartus II software through the Disable nCS and OE pull-ups on configuration device option. |
| Pin Name | Pin Type | Description |
|---|---|---|
| A[20..0] | Input | These pins are the address input to the flash memory for read and write operations. The addresses are internally latched during a write cycle. When the external flash interface is not used, leave these pins floating (with a few exceptions 4). These flash address, data, and control pins are internally connected to the configuration controller. In the 100-pin PQFP package, four address pins (A0, A1, A15, A16) are not internally connected to the controller. These loop-back connections must be made on the board between the C-A[] and F-A[] pins even when you are not using the external flash interface. All other address pins are connected internal to the package. All address pins are connected internally in the 88-pin UFBGA package. Pin A20 in EPC16 devices, pins A20 and A19 in EPC8 devices, and pins A20, A19, and A18 in EPC4 devices are NC pins. These pins should be left floating on the board. |
| DQ[15..0] | Bidirectional | This is the flash data bus interface between the flash memory and the controller. The controller or an external source drives DQ[15..0] during the flash command and the data write bus cycles. During the data read cycle, the flash memory drives the DQ[15..0] to the controller or external device. Leave these pins floating on the board when the external flash interface is not used. |
| CE# | Input | Active low flash input pin that activates the flash memory when asserted. When it is high, it deselects the device and reduces power consumption to standby levels. This flash input pin is internally connected to the controller. Leave this pin floating on the board when the external flash interface is not used. |
| RP#4 | Input | Active low flash input pin that resets the flash when asserted. When high, it enables normal operation. When low, it inhibits write operation to the flash memory, which provides data protection during power transitions. This flash input is not internally connected to the controller. Hence, an external loop-back connection between C-RP# and F-RP# must be made on the board even when you are not using the external flash interface. When using the external flash interface, connect the external device to the RP# pin with the loop back. Always tri-state RP# when the flash is not in use. |
| OE# | Input | Active-low flash-control input that is asserted by the controller or external device during flash read cycles. When asserted, it enables the drivers of the flash output pins. Leave this pin floating on the board when the external flash interface is not used. |
| WE#4 | Input | Active-low flash-write strobe asserted by the controller or external device during flash write cycles. When asserted, it controls writes to the flash memory. In the flash memory, addresses and data are latched on the rising edge of the WE# pulse. This flash input is not internally connected to the controller. Hence, an external loop-back connection between C-WE# and F-WE# must be made on the board even when you are not using the external flash interface. When using the external flash interface, connect the external device to the WE# pin with the loop back. |
| WP# | Input | Usually tied to VCC or GND on the board. The controller does not drive this pin because it could cause contention. Connection to VCC is recommended for faster block erase or programming times and to allow programming of the flash-bottom boot block, which is required when programming the device using the Quartus II software. This pin should be connected to VCC even when the external flash interface is not used. |
| VCCW | Supply | Block erase, full-chip erase, word write, or lock-bit configuration power supply. Connect this pin to the 3.3-V VCC supply, even when you are not using the external flash interface. |
| RY/BY# | Open-Drain Output | Flash asserts this pin when a write or erase operation is complete. This pin is not connected to the controller. RY/BY# is only available in Sharp flash-based EPC8 and EPC16.5 Leave this pin floating when the external flash interface is not used. |
| BYTE# | Input | Flash byte-enable pin and is only available for EPC devices in the 100-pin PQFP package. This pin must be connected to VCC on the board even when you are not using the external flash interface (the controller uses the flash in 16-bit mode). For Intel flash-based EPC device, this pin is connected to the VCCQ of the Intel flash die internally. Therefore, BYTE# must be connected directly to VCC without using any pull-up resistor. |
| Pin Name | Pin Type | Description |
|---|---|---|
| TDI | Input | JTAG data input pin. Connect this pin to VCC if the JTAG circuitry is not used. |
| TDO | Output | JTAG data output pin. Do not connect this pin if the JTAG circuitry is not used (leave this pin floating). |
| TCK | Input | JTAG clock pin. Connect this pin to GND if the JTAG circuitry is not used. |
| TMS | Input | JTAG mode select pin. Connect this pin to VCC if the JTAG circuitry is not used. |
| PGM[2..0] | Input | These three input pins select one of the eight pages of configuration data to configure the FPGAs in the system. Connect these pins on the board to select the page specified in the Quartus II software when generating the EPC device POF. PGM[2] is the MSB. The default selection is page 0;PGM[2..0]=000. These pins must not be left floating. |
| EXCLK | Input | Optional external clock input pin that can be used to generate the configuration clock (DCLK). When an external clock source is not used, connect this pin to a valid logic level (high or low) to prevent a floating-input buffer. If EXCLK is used, toggling the EXCLK input pin after the FPGA enters user mode will not effect the EPC device operation. |
| PORSEL | Input | This pin selects a 2-ms or 100-ms POR counter delay during power up. When PORSEL is low, POR time is 100 ms. When PORSEL is high, POR time is 2 ms. This pin must be connected to a valid logic level. |
| TM0 | Input | For normal operation, this test pin must be connected to GND. |
| TM1 | Input | For normal operation, this test pin must be connected to VCC. |
4 These pins can be driven to 12 V during production testing of the flash memory. Since the controller cannot tolerate the 12-V level, connections from the controller to these pins are not made internal to the package. Instead they are available as two separate pins. You must connect the two pins at the board level (for example, on the PCB, connect the C-WE# pin from controller to F-WE# pin from the flash memory).
5 For more information, refer to the PCN0506: Addition of Intel Flash Memory As Source For EPC4, EPC8 and EPC16 Enhanced Configuration Devices and Using the Intel Flash Memory-Based EPC4, EPC8 and EPC16 white paper.