Enhanced Configuration (EPC) Devices Datasheet

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ID 683253
Date 5/04/2016
Public
Document Table of Contents
Document Table of Contents x
1. Enhanced Configuration (EPC) Devices Datasheet
1. Enhanced Configuration (EPC) Devices Datasheet x
1.1. Supported Devices 1.2. Features 1.3. Functional Description 1.4. Pin Description 1.5. Power-On Reset 1.6. Power Sequencing 1.7. Programming and Configuration File Support 1.8. IEEE Std. 1149.1 (JTAG) Boundary-Scan 1.9. Timing Information 1.10. Operating Conditions 1.11. Package 1.12. Document Revision History
1.3. Functional Description x
1.3.1. FPGA Configuration 1.3.2. External Flash Interface 1.3.3. Intel Flash-Based EPC Device Protection 1.3.4. Dynamic Configuration (Page Mode) 1.3.5. Real-Time Decompression 1.3.6. Programmable Configuration Clock 1.3.7. Flash In-System Programming (ISP)
1.3.1. FPGA Configuration x
1.3.1.1. Configuration Signals 1.3.1.2. Fast Passive Parallel Configuration 1.3.1.3. Passive Serial Configuration 1.3.1.4. Concurrent Configuration
1.3.7. Flash In-System Programming (ISP) x
1.3.7.1. JTAG-based Programming 1.3.7.2. Programming using External Flash Interface
1.11. Package x
1.11.1. Package Layout Recommendation
1. Enhanced Configuration (EPC) Devices Datasheet

1.3.1.3. Passive Serial Configuration

APEX 20KC, APEX 20KE, APEX 20K, APEX II, Cyclone series, FLEX 10K, and Stratix series devices can be configured using EPC devices in the PS mode. This mode is similar to the FPP mode, with the exception that only one bit of data (DATA[0]) is transmitted to the FPGA per DCLK cycle. The remaining DATA[7..1] output pins are unused in this mode and driven low.

The configuration schematic for PS configuration of a single FPGA or single-serial chain is identical to the FPP schematic, with the exception that only DATA[0] output from the EPC device connects to the FPGA DATA0 input pin and the remaining DATA[7..1] pins are left floating.

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