Visible to Intel only — GUID: sss1452752568591
Ixiasoft
1.1. Supported Devices
1.2. Features
1.3. Functional Description
1.4. Pin Description
1.5. Power-On Reset
1.6. Power Sequencing
1.7. Programming and Configuration File Support
1.8. IEEE Std. 1149.1 (JTAG) Boundary-Scan
1.9. Timing Information
1.10. Operating Conditions
1.11. Package
1.12. Document Revision History
Visible to Intel only — GUID: sss1452752568591
Ixiasoft
1.3.1.2. Fast Passive Parallel Configuration
Stratix series and APEX II devices can be configured using the EPC device in the FPP configuration mode. In this mode, the EPC device sends a byte of data on the DATA[7..0] pins, which connect to the DATA[7..0] input pins of the FPGA, per DCLK cycle. Stratix series and APEX II FPGAs receive byte-wide configuration data per DCLK cycle. The following figure shows the EPC device in FPP configuration mode. In this figure, the external flash interface is not used and hence most flash pins are left unconnected (with the few noted exceptions).
Figure 2. FPP Configuration Connection Guideline
Multiple FPGAs can be configured using a single EPC device in FPP mode. In this mode, multiple Stratix series FPGAs, APEX II FPGAs, or both, are cascaded together in a daisy chain.
After the first FPGA completes configuration, its nCEO pin asserts to activate the nCE pin for the second FPGA, which prompts the second device to start capturing configuration data. In this setup, the FPGAs CONF_DONE pins are tied together, and hence all devices initialize and enter user mode simultaneously. If the EPC device or one of the FPGAs detects an error, configuration stops (and simultaneously restarts) for the whole chain because the nSTATUS pins are tied together.
Note: While Altera FPGAs can be cascaded in a configuration chain, the EPC devices cannot be cascaded to configure larger devices or chains.
Related Information