Enhanced Configuration (EPC) Devices Datasheet

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ID 683253
Date 5/04/2016
Public
Document Table of Contents
Document Table of Contents x
1. Enhanced Configuration (EPC) Devices Datasheet
1. Enhanced Configuration (EPC) Devices Datasheet x
1.1. Supported Devices 1.2. Features 1.3. Functional Description 1.4. Pin Description 1.5. Power-On Reset 1.6. Power Sequencing 1.7. Programming and Configuration File Support 1.8. IEEE Std. 1149.1 (JTAG) Boundary-Scan 1.9. Timing Information 1.10. Operating Conditions 1.11. Package 1.12. Document Revision History
1.3. Functional Description x
1.3.1. FPGA Configuration 1.3.2. External Flash Interface 1.3.3. Intel Flash-Based EPC Device Protection 1.3.4. Dynamic Configuration (Page Mode) 1.3.5. Real-Time Decompression 1.3.6. Programmable Configuration Clock 1.3.7. Flash In-System Programming (ISP)
1.3.1. FPGA Configuration x
1.3.1.1. Configuration Signals 1.3.1.2. Fast Passive Parallel Configuration 1.3.1.3. Passive Serial Configuration 1.3.1.4. Concurrent Configuration
1.3.7. Flash In-System Programming (ISP) x
1.3.7.1. JTAG-based Programming 1.3.7.2. Programming using External Flash Interface
1.11. Package x
1.11.1. Package Layout Recommendation
1. Enhanced Configuration (EPC) Devices Datasheet

1.3.6. Programmable Configuration Clock

The configuration clock (DCLK) speed is user programmable. One of two clock sources can be used to synthesize the configuration clock; a programmable oscillator or an external clock input pin (EXCLK). The configuration clock frequency can be further synthesized using the clock divider circuitry. This clock can be divided by the N counter to generate your DCLK output. The N divider supports all integer dividers between 1 and 16, as well as a 1.5 divider and a 2.5 divider. The duty cycle for all clock divisions other than non-integer divisions is 50% (for the non-integer dividers, the duty cycle will not be 50%).

Figure 5. Clock Divider UnitThe DCLK frequency is limited by the maximum DCLK frequency the FPGA supports.
Note: For more information about the maximum DCLK input frequency supported by the FPGA, refer to the configuration chapter in the appropriate device handbook.

The controller chip features a programmable oscillator that can output four different frequencies. The various settings generate clock outputs at frequencies as high as 10, 33, 50, and 66 MHz.

Table 7.  Internal Oscillator Frequencies
Frequency Setting Min (MHz) Typ (MHz) Max (MHz)
10 6.4 8.0 10.0
33 21.0 26.5 33.0
50 32.0 40.0 50.0
66 42.0 53.0 66.0

Clock source, oscillator frequency, and clock divider (N) settings can be made in the Quartus II software, by accessing the Configuration Device Options inside the Device Settings window or the Convert Programming Files window. The same window can be used to select between the internal oscillator and the external clock (EXCLK) input pin as your configuration clock source. The default setting selects the internal oscillator at the 10 MHz setting as the clock source, with a divide factor of 1.

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