Nios II Custom Instruction User Guide

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ID 683242
Date 4/27/2020
Public
Document Table of Contents
Document Table of Contents x
1. Nios II Custom Instruction Overview 2. Custom Instruction Hardware Interface 3. Custom Instruction Software Interface 4. Design Example: Cyclic Redundancy Check 5. Introduction to Nios® II Floating Point Custom Instructions 6. Nios II Floating Point Hardware 2 Component 7. Nios® II Floating Point Hardware (FPH1) Component 8. Document Revision History for Nios II Custom Instruction User Guide
1. Nios II Custom Instruction Overview x
1.1. Custom Instruction Implementation
1.1. Custom Instruction Implementation x
1.1.1. Custom Instruction Hardware Implementation 1.1.2. Custom Instruction Software Implementation
2. Custom Instruction Hardware Interface x
2.1. Custom Instruction Types
2.1. Custom Instruction Types x
2.1.1. Combinational Custom Instructions 2.1.2. Multicycle Custom Instructions 2.1.3. Extended Custom Instructions 2.1.4. Internal Register File Custom Instructions 2.1.5. External Interface Custom Instructions
2.1.1. Combinational Custom Instructions x
2.1.1.1. Combinational Custom Instruction Ports 2.1.1.2. Combinational Custom Instruction Timing
2.1.2. Multicycle Custom Instructions x
2.1.2.1. Multicycle Custom Instruction Ports 2.1.2.2. Multicycle Custom Instruction Timing
2.1.3. Extended Custom Instructions x
2.1.3.1. Extended Custom Instruction Timing
2.1.4. Internal Register File Custom Instructions x
2.1.4.1. Internal Register File Custom Instruction Example 2.1.4.2. Internal Register File Custom Instruction Ports
3. Custom Instruction Software Interface x
3.1. Custom Instruction Software Examples 3.2. Built-in Functions and User-defined Macros 3.3. Custom Instruction Assembly Language Interface
3.2. Built-in Functions and User-defined Macros x
3.2.1. Built-in Functions with No Return Value 3.2.2. Built-in Functions that Return a Value of Type Int 3.2.3. Built-in Functions that Return a Value of Type Float 3.2.4. Built-in Functions that Return a Pointer Value
3.3. Custom Instruction Assembly Language Interface x
3.3.1. Custom Instruction Assembly Language Syntax 3.3.2. Custom Instruction Assembly Language Examples 3.3.3. Custom Instruction Word Format
3.3.3. Custom Instruction Word Format x
3.3.3.1. Select Index Field (N)
4. Design Example: Cyclic Redundancy Check x
4.1. Building the CRC Example Hardware 4.2. Building the CRC Example Software
4.1. Building the CRC Example Hardware x
4.1.1. Setting up the Environment for the CRC Example Design 4.1.2. Opening the Component Editor 4.1.3. Specifying the Custom Instruction Component Type 4.1.4. Displaying the Custom Instruction Block Symbol 4.1.5. Adding the CRC Custom Instruction HDL Files 4.1.6. Configuring the Custom Instruction Parameter Type 4.1.7. Setting Up the CRC Custom Instruction Interfaces 4.1.8. Configuring the Custom Instruction Signal Type 4.1.9. Saving and Adding the CRC Custom Instruction 4.1.10. Generating and Compiling the CRC Example System
4.1.7. Setting Up the CRC Custom Instruction Interfaces x
4.1.7.1. Specifying Additional Interfaces
4.2. Building the CRC Example Software x
4.2.1. Running and Analyzing the CRC Example Software 4.2.2. Using the User-defined Custom Instruction Macro
4.2.1. Running and Analyzing the CRC Example Software x
4.2.1.1. Output of the CRC Design Example Software Run on a Cyclone V E FPGA Development Kit using the Intel® Quartus® Prime Software v15.1.
5. Introduction to Nios® II Floating Point Custom Instructions x
5.1. Floating Point Background 5.2. IEEE 754 Format 5.3. Rounding Schemes 5.4. Special Floating Point Cases
5.2. IEEE 754 Format x
5.2.1. Unit in the Last Place 5.2.2. Floating Point Value Encoding
5.3. Rounding Schemes x
5.3.1. Nearest Rounding 5.3.2. Truncation Rounding 5.3.3. Faithful Rounding 5.3.4. Rounding Examples
6. Nios II Floating Point Hardware 2 Component x
6.1. Overview of the Floating Point Hardware 2 Component 6.2. Floating Point Hardware 2 IEEE 754 Compliance 6.3. IEEE 754 Exception Conditions with FPH2 6.4. Floating Point Hardware 2 Operations 6.5. Building the FPH2 Example Hardware 6.6. Building the FPH2 Example Software 6.7. FPH2 Implementation of GCC Options 6.8. Nios II FPH2 and the Newlib Library 6.9. C Macros for round(), fmins(), and fmaxs()
6.6. Building the FPH2 Example Software x
6.6.1. FPH2 and Nios II GCC 6.6.2. Floating Point Hardware 2 Conversions 6.6.3. Nios II FPH2 Software Options
6.6.3. Nios II FPH2 Software Options x
6.6.3.1. -mcustom-<operation> 6.6.3.2. Nios II FPH2 Pragmas 6.6.3.3. -mcustom-fpu-cfg
6.7. FPH2 Implementation of GCC Options x
6.7.1. -fno-math-errno 6.7.2. -fsingle-precision-constant 6.7.3. -funsafe-math-optimizations 6.7.4. -ffinite-math-only 6.7.5. -fno-trapping-math 6.7.6. -frounding-math
7. Nios® II Floating Point Hardware (FPH1) Component x
7.1. Creating the FPH1 Example Hardware 7.2. Adding FPH1 to the Design and Configuring the Device 7.3. Building the FPH1 Example Software 7.4. Nios II FPH1 and the Newlib Library 7.5. Assessing Your Floating Point Optimization Needs 7.6. Hardware Divide Considerations with FPH1
7.3. Building the FPH1 Example Software x
7.3.1. Creating the FPH1 Software Project 7.3.2. Running and Analyzing the FPH1 Example Software 7.3.3. Software Implementation for FPH1
1. Nios II Custom Instruction Overview
2. Custom Instruction Hardware Interface
3. Custom Instruction Software Interface
4. Design Example: Cyclic Redundancy Check
5. Introduction to Nios® II Floating Point Custom Instructions
6. Nios II Floating Point Hardware 2 Component
7. Nios® II Floating Point Hardware (FPH1) Component
8. Document Revision History for Nios II Custom Instruction User Guide

5. Introduction to Nios® II Floating Point Custom Instructions

The Nios II architecture supports single precision floating point instructions with either of two optional components:
  • Floating point hardware 22 (FPH2)—This component supports floating point instructions as specified by the IEEE Std 754-2008 but with simplified, non-standard rounding modes. The basic set of floating point custom instructions includes single precision floating point addition, subtraction, multiplication, division, square root, integer to float conversion, float to integer conversion, minimum, maximum, negate, absolute, and comparisons.
  • Floating point hardware (FPH1)—This component supports floating point instructions as specified by the IEEE Std 754-1985. The basic set of floating point custom instructions includes single-precision floating point addition, subtraction, and multiplication. Floating point division is available as an extension to the basic instruction set.
    Note: For optimum performance and device footprint, Intel recommends using FPH2 rather than FPH1.

These floating point instructions are implemented as custom instructions. The table below lists a detailed description of the conformance to the IEEE standards.

Table 8.  Hardware Conformance with IEEE 754-1985 and IEEE 754-2008 Floating Point Standard
Feature Floating Point Hardware Implementation with IEEE 754-1985 Floating Point Hardware 2 Implementation with IEEE 754-2008
Operations Addition/subtraction Implemented Implemented
Multiplication Implemented Implemented
Division Optional Implemented
Square root Not implemented, this operation is implemented in software. Implemented
Integer to float/float to integer Not implemented, this operation is implemented in software. Implemented
Minimum/maximum Not implemented, this operation is implemented in software. Implemented
Negate/absolute Not implemented, this operation is implemented in software. Implemented
Comparisons Not implemented, this operation is implemented in software. Implemented
Precision Single Implemented Implemented
Double Not implemented. Double precision operations are implemented in software. Not implemented. Double precision operations are implemented in software.
Exception conditions Invalid operation Result is Not a Number (NaN) Result is Not a Number (NaN)
Division by zero Result is ±infinity Result is ±infinity
Overflow Result is ±infinity Result is ±infinity
Inexact Result is a normal number Result is a normal number
Underflow Result is ±0 Result is ±0
Rounding Modes Round to nearest Implemented Implemented (roundTiesToAway mode)
Round toward zero Not implemented Implemented (truncation mode)
Round toward +infinity Not implemented Not implemented
Round toward –infinity Not implemented Not implemented
NaN Quiet Implemented No distinction is made between signaling and quiet NaNs as input operands. A result that produces a NaN may produce either a signaling or quiet NaN.
Signaling Not implemented
Subnormal (denormalized) numbers   Subnormal operands are treated as zero. The FPH2 custom instructions do not generate subnormal numbers.
  • The comparison, minimum, maximum, negate, and absolute operations support subnormal numbers.
  • The add, subtract, multiply, divide, square root, and float to integer operations do NOT support subnormal numbers. Subnormal operands are treated as signed zero. The FPH1 custom instructions do not generate subnormal numbers.3
  • The integer to float operation cannot create subnormal numbers.
Software exceptions   Not implemented. IEEE 754-1985 exception conditions are detected and handled as described elsewhere in this table. Not implemented. IEEE 754-2008 exception conditions are detected and handled as described elsewhere in this table.3
Status flags   Not implemented. IEEE 754-1985 exception conditions are detected and handled as described elsewhere in this table. Not implemented. IEEE 754-2008 exception conditions are detected and handled as described elsewhere in this table.3
Note: The FPH2 component also supports faithful rounding, which is not an IEEE 754-defined rounding mode. Faithful rounding rounds results to either the upper or lower nearest single-precision numbers. Therefore, the result produced is one of two possible values and the choice between the two is not defined. The maximum error of faithful rounding is 1 unit in the last place (ulp). Errors may not be evenly distributed.

Section Content
Floating Point Background
IEEE 754 Format
Rounding Schemes
Special Floating Point Cases

2 Second generation
3 This operation is not fully compliant with IEEE 754-2008.
Level Two Title