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2.1. Compilation Overview
2.2. Using the Compilation Dashboard
2.3. Design Netlist Infrastructure (Beta)
2.4. Design Synthesis
2.5. Design Place and Route
2.6. Incremental Optimization Flow
2.7. Fast Forward Compilation Flow
2.8. Full Compilation Flow
2.9. Exporting Compilation Results
2.10. Integrating Other EDA Tools
2.11. Synthesis Language Support
2.12. Compiler Optimization Techniques
2.13. Synthesis Settings Reference
2.14. Fitter Settings Reference
2.15. Design Compilation Revision History
2.9.1. Exporting a Version-Compatible Compilation Database
2.9.2. Importing a Version-Compatible Compilation Database
2.9.3. Creating a Design Partition
2.9.4. Exporting a Design Partition
2.9.5. Reusing a Design Partition
2.9.6. Viewing Quartus Database File Information
2.9.7. Clearing Compilation Results
3.1. Factors Affecting Compilation Results
3.2. Strategies to Reduce the Overall Compilation Time
3.3. Reducing Synthesis Time and Synthesis Netlist Optimization Time
3.4. Reducing Placement Time
3.5. Reducing Routing Time
3.6. Reducing Static Timing Analysis Time
3.7. Setting Process Priority
3.8. Reducing Compilation Time Revision History
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2.4.1. Running Synthesis
Run design synthesis as part of a full compilation, or as an independent process. Before running synthesis, specify settings that control synthesis processing. The Messages window dynamically displays processing information, warnings, or errors. Following Analysis & Synthesis processing, the Synthesis report provides detailed information about the synthesis of your project. To run synthesis, perform the following steps.
- Create or open an Intel® Quartus® Prime project with valid design files for compilation.
- Before running synthesis, specify any of the following settings and constraints that impact synthesis:
- To specify options for the synthesis of Verilog HDL input files, click Assignments > Settings > Verilog HDL Input.
- To specify options for the synthesis of VHDL input files, click Assignments > Settings > VHDL Input.
- To specify options that affect compilation processing time, click Assignments > Settings > Compilation Process Settings.
- To specify the Compiler's high-level optimization strategy and other options, click Assignments > Settings > Compiler Settings. Specify the optimization goal, according to Compiler Optimization Modes.
- On the Compiler Settings page enable or disable the Enable Intermediate Fitter Snapshots option to preserve snapshots for the Plan, Place, Route, and Retime stages any time you run full compilation. The Compiler does not generate intermediate snapshots by default.
- To specify advanced synthesis settings, click Assignments > Settings > Compiler Settings, and then click Advanced Settings (Synthesis).
- Consider enabling fractal synthesis for arithmetic-intensive designs that exhaust all DSP resources, according to the guidelines in Fractal Synthesis Optimization.
- To run synthesis, click Synthesis on the Compilation Dashboard.
Section Content
Preserving Registers During Synthesis
Preserving Signals for Monitoring and Debugging
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