Intel® Quartus® Prime Pro Edition User Guide: Design Compilation

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Date 9/26/2022
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Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Design Compilation 3. Reducing Compilation Time 4. Intel® Quartus® Prime Pro Edition User Guide Design Compilation Archives A. Intel® Quartus® Prime Pro Edition User Guides
2. Design Compilation x
2.1. Compilation Overview 2.2. Using the Compilation Dashboard 2.3. Design Netlist Infrastructure (Beta) 2.4. Design Synthesis 2.5. Design Place and Route 2.6. Incremental Optimization Flow 2.7. Fast Forward Compilation Flow 2.8. Full Compilation Flow 2.9. Exporting Compilation Results 2.10. Integrating Other EDA Tools 2.11. Synthesis Language Support 2.12. Compiler Optimization Techniques 2.13. Synthesis Settings Reference 2.14. Fitter Settings Reference 2.15. Design Compilation Revision History
2.1. Compilation Overview x
2.1.1. Compilation Flows 2.1.2. Compilation Hierarchy 2.1.3. Compilation Monitoring
2.3. Design Netlist Infrastructure (Beta) x
2.3.1. Exploring the RTL Analyzer (Beta) 2.3.2. Early Timing Analysis (Beta) 2.3.3. DNI Use Case Examples
2.3.1. Exploring the RTL Analyzer (Beta) x
2.3.1.1. Sweep Hints Viewer Hierarchy View Sweep Hints View Identifying the Root Cause of Swept Objects Viewing Related Swept Objects 2.3.1.2. Connectivity Tracer 2.3.1.3. Object Set Console 2.3.1.4. Module Interfaces 2.3.1.5. Bundled Instances 2.3.1.6. Auto-hide Unconnected Pins
2.3.2. Early Timing Analysis (Beta) x
2.3.2.1. Synopsys* Design Constraint (SDC) on RTL 2.3.2.2. Post-Synthesis Static Timing Analysis (STA) 2.3.2.3. Types of SDC Files Used in the Intel® Quartus® Prime Software
2.3.2.1. Synopsys* Design Constraint (SDC) on RTL x
2.3.2.1.1. Registering the SDC-on-RTL SDC File 2.3.2.1.2. Applying the SDC-on-RTL Constraints 2.3.2.1.3. Inspecting SDC-on-RTL Constraints 2.3.2.1.4. Creating Constraints in SDC-on-RTL SDC Files
2.3.3. DNI Use Case Examples x
2.3.3.1. Scripting Routine Tasks Using DNI Tcl Commands 2.3.3.2. Traversing the DNI Netlist Using Tcl Commands
2.4. Design Synthesis x
2.4.1. Running Synthesis 2.4.2. Viewing Synthesis Reports 2.4.3. Viewing Synthesis Dynamic Report
2.4.1. Running Synthesis x
2.4.1.1. Preserving Registers During Synthesis 2.4.1.2. Preserving Signals for Monitoring and Debugging
2.5. Design Place and Route x
2.5.1. Running the Fitter 2.5.2. Viewing Fitter Reports
2.5.1. Running the Fitter x
2.5.1.1. Fitter Commands 2.5.1.2. Disabling or Enabling Physical Synthesis Optimization
2.5.2. Viewing Fitter Reports x
2.5.2.1. Plan Stage Reports 2.5.2.2. Place Stage Reports 2.5.2.3. Route Stage Reports 2.5.2.4. Retime Stage Reports 2.5.2.5. Finalize Stage Reports
2.5.2.2. Place Stage Reports x
2.5.2.2.1. Global Signal Visualization Report
2.5.2.3. Route Stage Reports x
2.5.2.3.1. Global Router Congestion Hotspot Summary Report 2.5.2.3.2. Global Router Wire Utilization Map Report
2.6. Incremental Optimization Flow x
2.6.1. Concurrent Analysis During Synthesis or Fitting 2.6.2. Analyzing Compiler Snapshots 2.6.3. Validating Periphery (I/O) after the Plan Stage
2.6.2. Analyzing Compiler Snapshots x
2.6.2.1. Running Snapshot Viewer
2.6.2.1. Running Snapshot Viewer x
2.6.2.1.1. Analyzing Failing Paths with Snapshot Viewer 2.6.2.1.2. Analyzing Clocking with Snapshot Viewer 2.6.2.1.3. Analyzing High Fan-out Nets with Snapshot Viewer 2.6.2.1.4. Validating Timing Constraints with Snapshot Viewer 2.6.2.1.5. Analyzing Congestion with Snapshot Viewer
2.7. Fast Forward Compilation Flow x
2.7.1. Step 1: Run Register Retiming 2.7.2. Step 2: Review Retiming Results 2.7.3. Step 3: Run Fast Forward Compile 2.7.4. Step 4: Review Fast Forward Results 2.7.5. Step 5: Implement Fast Forward Recommendations 2.7.6. Retiming Restrictions and Workarounds
2.7.2. Step 2: Review Retiming Results x
2.7.2.1. Locate Critical Chains
2.7.3. Step 3: Run Fast Forward Compile x
2.7.3.1. Fast Forward Compile By Hierarchy 2.7.3.2. HyperFlex Settings
2.7.4. Step 4: Review Fast Forward Results x
2.7.4.1. Clock Fmax Summary Report 2.7.4.2. Fast Forward Details Report
2.8. Full Compilation Flow x
2.8.1. Full Compilation Flow with Temporary Optimization Mode
2.9. Exporting Compilation Results x
2.9.1. Exporting a Version-Compatible Compilation Database 2.9.2. Importing a Version-Compatible Compilation Database 2.9.3. Creating a Design Partition 2.9.4. Exporting a Design Partition 2.9.5. Reusing a Design Partition 2.9.6. Viewing Quartus Database File Information 2.9.7. Clearing Compilation Results
2.9.6. Viewing Quartus Database File Information x
2.9.6.1. QDB File Attribute Types
2.10. Integrating Other EDA Tools x
2.10.1. Generating a VQM Netlist for other EDA Tools
2.11. Synthesis Language Support x
2.11.1. Verilog and SystemVerilog Synthesis Support 2.11.2. VHDL Synthesis Support
2.11.1. Verilog and SystemVerilog Synthesis Support x
2.11.1.1. Verilog HDL Input Settings (Settings Dialog Box) 2.11.1.2. Design Libraries 2.11.1.3. Verilog HDL Configuration 2.11.1.4. Initial Constructs and Memory System Tasks 2.11.1.5. Verilog HDL Macros
2.11.1.3. Verilog HDL Configuration x
2.11.1.3.1. Hierarchical Design Configurations
2.11.2. VHDL Synthesis Support x
2.11.2.1. VHDL Input Settings (Settings Dialog Box) 2.11.2.2. VHDL Standard Libraries and Packages 2.11.2.3. VHDL wait Constructs 2.11.2.4. VHDL-2019 Conditional Analysis Tool Directives
2.12. Compiler Optimization Techniques x
2.12.1. Compiler Optimization Modes 2.12.2. Allow Register Retiming 2.12.3. Automatic Gated Clock Conversion 2.12.4. Enable Intermediate Fitter Snapshots 2.12.5. Fast Preserve Option 2.12.6. Fractal Synthesis Optimization
2.12.6. Fractal Synthesis Optimization x
2.12.6.1. Enabling or Disabling Fractal Synthesis
2.13. Synthesis Settings Reference x
2.13.1. Advanced Synthesis Settings
3. Reducing Compilation Time x
3.1. Factors Affecting Compilation Results 3.2. Strategies to Reduce the Overall Compilation Time 3.3. Reducing Synthesis Time and Synthesis Netlist Optimization Time 3.4. Reducing Placement Time 3.5. Reducing Routing Time 3.6. Reducing Static Timing Analysis Time 3.7. Setting Process Priority 3.8. Reducing Compilation Time Revision History
3.2. Strategies to Reduce the Overall Compilation Time x
3.2.1. Running the ECO Compilation Flow 3.2.2. Enabling Multi-Processor Compilation 3.2.3. Using Block-Based Compilation
3.3. Reducing Synthesis Time and Synthesis Netlist Optimization Time x
3.3.1. Settings to Reduce Synthesis Time and Synthesis Netlist Optimization Time 3.3.2. Use Appropriate Coding Style to Reduce Synthesis Time
3.4. Reducing Placement Time x
3.4.1. Placement Effort Multiplier Settings
3.5. Reducing Routing Time x
3.5.1. Identifying Routing Congestion with the Chip Planner
3.5.1. Identifying Routing Congestion with the Chip Planner x
3.5.1.1. Areas with Routing Congestion 3.5.1.2. Congestion due to HDL Coding style
1. Answers to Top FAQs
2. Design Compilation
3. Reducing Compilation Time
4. Intel® Quartus® Prime Pro Edition User Guide Design Compilation Archives
A. Intel® Quartus® Prime Pro Edition User Guides

2.3.1.1. Sweep Hints Viewer

Sweep Hints Viewer is one of the RTL Analyzer tools you can access from the menu by selecting Tools > View Sweep Hints. It allows you to understand why Synthesis removed a logic in your design.

Hierarchy View

Recall from the DNI Flow (Beta) how sweep optimization (Swept checkpoint) happens as part of the Analysis & Elaboration stage. The sweep optimization phase leaves behind a database of objects that were swept away and the reason for their removal. The database also tracks relationships between the removed objects. For example, if an output of a gate is dangling, it is swept away. Few cells in the fan-in cone can also be swept away because their output does not drive anything useful. The Sweep Hints Viewer allows you to view the sweep hints database with a list of marked objects in the pre-swept design that are removed later.

Note: For large and complex designs, the total number of swept objects can be significant (in millions). Hence, the swept objects are hierarchically arranged so that you can query, filter, and find regions of your interest quickly.
Figure 9. Hierarchy Tab in the Sweep Hints Viewer

Within the Hierarchy tab of the Sweep Hints Viewer, you can observe various hierarchy levels and their sweep statistics. The logic unit here is a leaf cell, which refers to logical primitives, such as AND/OR gate or registers. A hierarchical cell is a composite of leaf cells and other hierarchical cells.

The Leaf Cells Count by Hierarchy table in the above image provides information about the percentage of the logic swept either locally or in the full hierarchy of a given hierarchical path. The table columns for the number of leaf cells indicate before and after a sweep and the type of hierarchical path, which can be USER (RTL you designed), Intel® IP, or MEGAFUNCTION ( Intel® -provided library modules). If the hierarchy table is large, use the filter options to refine the regions of your design.

Note: Intel® IP and MEGAFUNCTION types are hidden by default since you cannot modify them. However, you can view them in specific circumstances by selecting the desired option in the Hierarchy Type drop-down list. Encrypted modules are always hidden from this view.

Sweep Hints View

Figure 10. Example of Swept Objects in the Sweep Hints Viewer

Notice the swept object highlighted with the teal color in the schematic view. If you hover over this object tool-tip or view the sweep reason in the Sweep Hints Viewer, you can see that this instance was swept away because the instance port lost fanout. Similarly, you can select other swept objects to identify their root cause and view them in the schematic view and hierarchy view. All these objects are eventually swept away from the design when you proceed with the compilation flow.

While the Hierarchy tab helps in filtering by sweep statistics of an instance, the Sweep Hints tab allows you to filter and query the leaf objects swept away in a given hierarchy level. Various columns in the table describe the object involved in the sweep and provide ways to query data. For instance, you can look for specific instance types or limit the results to specific sweep reasons, types, and so on.

Identifying the Root Cause of Swept Objects

To identify the root cause for a particular node in the design being swept away, you must understand various reasons behind why a single node was marked during the sweep, as listed in the following:

  • A node stuck at constant 0 or 1. For example, an input port of an AND gate stuck at 0 triggers a sweep of the AND gate since the output of the AND gate is also stuck at 0.
  • A node behaved as a wire and was deleted. For example, a multiplexer whose select line is connected to constant acts as a wire​.
  • A node was modified during the sweep but it was not deleted.
  • A node lost all fan-outs and it was deleted.
  • A port or instance port got disconnected because the parent or child did not have a fan-out.

Viewing Related Swept Objects

You can also view related swept objects by right-clicking on a select object under Sweep Hints and selecting Show Hint Trace in the context-sensitive menu. Hint Trace for ID <number> section displays a hierarchical listing of swept objects that caused a particular object to be swept away and objects swept away as a result of one object. The ability to highlight and select various objects in the chain allows you to narrow down on the desired sweep information.

In the following figure, when you trace the sweep hints for a port with object ID 30, under Hint Trace for ID 30 , you notice an instance port with object ID 2 being related to the swept port 30. The sweep reason for both objects is disconnected fanout.

Figure 11. Related Swept Objects
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