Visible to Intel only — GUID: jbr1444415677885
Ixiasoft
Visible to Intel only — GUID: jbr1444415677885
Ixiasoft
2.11.1.1. Verilog HDL Input Settings (Settings Dialog Box)
Setting |
Description |
---|---|
Verilog Version |
Directs synthesis to process Verilog HDL input design files using the specified standard. You can select any of the supported language standards to match your Verilog HDL files or SystemVerilog design files. |
Library Mapping File |
Allows you to optionally specify a provided Library Mapping File (.lmf) for use in synthesizing Verilog HDL files that contain non-Intel FPGA functions mapped to IP cores. You can specify the full path name of the LMF in the File name box. |
Verilog HDL Macro | Verilog HDL macros are pre-compiler directives which can be added to Verilog HDL files to define constants, flags, or other features by Name and Setting. Macros that you add appear in the Existing Verilog HDL macro settings list. |