Serial Lite IV Intel® Stratix™ 10 FPGA IP Design Example User Guide

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ID 683223
Date 11/01/2021
Public
Document Table of Contents
Document Table of Contents x
1. About the Serial Lite IV Intel® Stratix® 10 FPGA IP Design Example User Guide 2. Quick Start Guide 3. Detailed Description for Serial Lite IV Design Example 4. Serial Lite IV Intel® Stratix® 10 FPGA IP Design Example User Guide Archives 5. Document Revision History for the Serial Lite IV Intel® Stratix® 10 FPGA IP Design Example User Guide
2. Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Compiling and Simulating the Design 2.5. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for Serial Lite IV Design Example x
3.1. Features 3.2. Design Example Components 3.3. Simulation 3.4. Hardware Testing 3.5. Error Handling 3.6. Link Debugging Sequence 3.7. Serial Lite IV IP Toolkit
3.2. Design Example Components x
3.2.1. Traffic Generator 3.2.2. Traffic Checker 3.2.3. DCFIFO 3.2.4. System Console 3.2.5. Demo Management 3.2.6. Demo Control
3.3. Simulation x
3.3.1. Simulation Results for Basic Mode 3.3.2. Simulation Result for Full Mode
3.4. Hardware Testing x
3.4.1. Hardware Testing Result for Basic Transfer Mode 3.4.2. Hardware Testing Result for Full Transfer Mode 3.4.3. Traffic Statistic Results
3.7. Serial Lite IV IP Toolkit x
3.7.1. Setting Up and Running the Toolkit 3.7.2. Toolkit GUI Settings
1. About the Serial Lite IV Intel® Stratix® 10 FPGA IP Design Example User Guide
2. Quick Start Guide
3. Detailed Description for Serial Lite IV Design Example
4. Serial Lite IV Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
5. Document Revision History for the Serial Lite IV Intel® Stratix® 10 FPGA IP Design Example User Guide

3.6. Link Debugging Sequence

The Serial Lite IV IP provides a link debugging sequence for TX and RX that you can use when debugging your design.
Figure 17. TX Link Debugging Flowchart
Table 12.  TX Link Debugging Signals
Signal Location Description
tx_link_up Top-level TX signal The IP asserts this signal to indicate that the initialization sequence is complete and the IP is ready to transmit the data.
tx_pll_locked Top-level PHY signal This active-high signal indicates that the transceivers are locked to the reference clock.
phy_tx_lanes_stable Top-level PHY signal The IP asserts this signal when TX datapath is ready to send data.
phy_ehip_ready[(n*2)-1:0] Top-level PHY signal The IP asserts this signal after the tx_pcs_fec_phy_reset_n and rx_pcs_fec_phy_reset_n signals deassert to indicate that the custom PCS has completed internal initialization and is ready for transmission.
Figure 18. RX Link Debugging Flowchart
Table 13.  RX Link Debugging Signals
Signal Location Description
rx_link_up Top-level RX signal The IP asserts this signal to indicate that the initialization sequence is complete, and the IP is ready to receive data.
phy_rx_pcs_ready[(n*2)-1:0] Top-level PHY signal The IP asserts this signal when RX datapath is ready to receive data.
phy_rx_block_lock[(n*2)-1:0] Top-level PHY signal The IP asserts this signal to indicate the 66b block alignment has completed for the lanes.
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