Serial Lite IV Intel® Stratix™ 10 FPGA IP Design Example User Guide

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ID 683223
Date 11/01/2021
Public
Document Table of Contents
Document Table of Contents x
1. About the Serial Lite IV Intel® Stratix® 10 FPGA IP Design Example User Guide 2. Quick Start Guide 3. Detailed Description for Serial Lite IV Design Example 4. Serial Lite IV Intel® Stratix® 10 FPGA IP Design Example User Guide Archives 5. Document Revision History for the Serial Lite IV Intel® Stratix® 10 FPGA IP Design Example User Guide
2. Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Compiling and Simulating the Design 2.5. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for Serial Lite IV Design Example x
3.1. Features 3.2. Design Example Components 3.3. Simulation 3.4. Hardware Testing 3.5. Error Handling 3.6. Link Debugging Sequence 3.7. Serial Lite IV IP Toolkit
3.2. Design Example Components x
3.2.1. Traffic Generator 3.2.2. Traffic Checker 3.2.3. DCFIFO 3.2.4. System Console 3.2.5. Demo Management 3.2.6. Demo Control
3.3. Simulation x
3.3.1. Simulation Results for Basic Mode 3.3.2. Simulation Result for Full Mode
3.4. Hardware Testing x
3.4.1. Hardware Testing Result for Basic Transfer Mode 3.4.2. Hardware Testing Result for Full Transfer Mode 3.4.3. Traffic Statistic Results
3.7. Serial Lite IV IP Toolkit x
3.7.1. Setting Up and Running the Toolkit 3.7.2. Toolkit GUI Settings
1. About the Serial Lite IV Intel® Stratix® 10 FPGA IP Design Example User Guide
2. Quick Start Guide
3. Detailed Description for Serial Lite IV Design Example
4. Serial Lite IV Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
5. Document Revision History for the Serial Lite IV Intel® Stratix® 10 FPGA IP Design Example User Guide

2.4. Compiling and Simulating the Design

The design example testbench simulates your generated design.
  1. Change the working directory to <example_design_directory>/ed_sim/<simulator>
    Note: In Serial Lite IV Intel® FPGA IP version 1.1.0, the ModelSim* simulator does not capture the top-level IP signals in the waveform. To capture the top-level IP signals, add the ld_debug command to the ed_sim/mentor/run_tb.tcl file.
  2. Run the simulation script for the simulator of your choice.
    Table 6.  Testbench Simulation Scripts
    Simulator File Directory Command
    ModelSim*
    Note: This IP only supports ModelSim* - Intel® FPGA Starter Edition simulator.
    		<variation name>seriallite4_0_example_design/ed_sim/mentor do run_tb.tcl
    QuestaSim*
    VCS* <variation name>seriallite4_0_example_design/ed_sim/synopsys/vcs sh run_tb.sh
    VCS* MX <variation name>seriallite4_0_example_design/ed_sim/synopsys/vcsmx sh run_tb.sh
    Xcelium* <variation name>seriallite4_0_example_design/ed_sim/xcelium sh run_tb.sh
  3. When the simulation is complete, you can now analyze the results and verify the design. A successful simulation ends with the following message, "Test Passed." 
#    ****************************** Data Forwarding Test Completed ****************************
#    
#    ************************************** Test Completed ************************************
#    
#    End time                       = 534579600
#    
#    Total words tranferred         = 10000
#    
#    Number of bursts               = 0
#    
#    Random number generator seed   = 1756255697
#    
#    Link Latency                   = 434 ns
#    
#    *************************************** Test Passed **************************************
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