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1. About the Serial Lite IV Intel® Stratix® 10 FPGA IP Design Example User Guide
2. Quick Start Guide
3. Detailed Description for Serial Lite IV Design Example
4. Serial Lite IV Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
5. Document Revision History for the Serial Lite IV Intel® Stratix® 10 FPGA IP Design Example User Guide
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3.2.6. Demo Control
The design example uses the demo control module to configure the transceiver and the demo management module. It has separate Avalon® memory-mapped interfaces connected to the transceiver reconfiguration block and the demo management module. The demo control module also has a JTAG master, parallel input/output (PIO) interface, and an In-system Source and Probe (ISSP) modules for debugging through system console.
This modules is only available in the hardware design example.