Serial Lite IV Intel® Stratix™ 10 FPGA IP Design Example User Guide

Download PDF
ID 683223
Date 11/01/2021
Public
Document Table of Contents
Document Table of Contents x
1. About the Serial Lite IV Intel® Stratix® 10 FPGA IP Design Example User Guide 2. Quick Start Guide 3. Detailed Description for Serial Lite IV Design Example 4. Serial Lite IV Intel® Stratix® 10 FPGA IP Design Example User Guide Archives 5. Document Revision History for the Serial Lite IV Intel® Stratix® 10 FPGA IP Design Example User Guide
2. Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Compiling and Simulating the Design 2.5. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for Serial Lite IV Design Example x
3.1. Features 3.2. Design Example Components 3.3. Simulation 3.4. Hardware Testing 3.5. Error Handling 3.6. Link Debugging Sequence 3.7. Serial Lite IV IP Toolkit
3.2. Design Example Components x
3.2.1. Traffic Generator 3.2.2. Traffic Checker 3.2.3. DCFIFO 3.2.4. System Console 3.2.5. Demo Management 3.2.6. Demo Control
3.3. Simulation x
3.3.1. Simulation Results for Basic Mode 3.3.2. Simulation Result for Full Mode
3.4. Hardware Testing x
3.4.1. Hardware Testing Result for Basic Transfer Mode 3.4.2. Hardware Testing Result for Full Transfer Mode 3.4.3. Traffic Statistic Results
3.7. Serial Lite IV IP Toolkit x
3.7.1. Setting Up and Running the Toolkit 3.7.2. Toolkit GUI Settings
1. About the Serial Lite IV Intel® Stratix® 10 FPGA IP Design Example User Guide
2. Quick Start Guide
3. Detailed Description for Serial Lite IV Design Example
4. Serial Lite IV Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
5. Document Revision History for the Serial Lite IV Intel® Stratix® 10 FPGA IP Design Example User Guide

2.3.1. Design Example Parameters

The Serial Lite IV IP parameter editor includes an Example Design tab for you to specify parameters before generating the design example.
Figure 4. Example Design Tab
Table 4.  Parameters in the Example Design Tab
Parameter Description
Generate Files for

The IP generates the necessary design example files for simulation and compilation.

Simulation—select this option to generate the necessary design simulation files.

Synthesis—select this option to generate the necessary design synthesis files. Use these files to compile the design in the Intel® Quartus® Prime Pro Edition software for hardware testing.

Generate Files for Synthesis

When selected, the IP generates the synthesis files. Use these files to compile the design in the Intel® Quartus® Prime Pro Edition software for hardware testing.

Generate File Format The format of the RTL files for simulation—Verilog or VHDL.
Select Board Supported hardware for design implementation. When you select an Intel FPGA development board, the Target Device is the one that matches the device on the Development Kit.

If this menu is grayed out, there is no supported board for the options that you select.

Stratix 10 TX Signal Integrity Development Kit: This option allows you to test the design example on the selected Intel FPGA IP development kit. This selection automatically selects the Target Device to match the device on the Intel FPGA IP development kit. If your board revision has a different speed grade, you can change the target device.

Custom Development Kit: This option allows you to test the design example on a third party development kit with Intel FPGA IP device, a custom designed board with Intel FPGA IP device, or a standard Intel FPGA IP development kit not available for selection. You can also select a custom device for the custom development kit.

No Development Kit: This option excludes the hardware aspects for the design example.

Change Target Device Select a different device grade for Intel FPGA IP development kit. For device-specific details, refer to the device datasheet on the Intel FPGA website.
Level Two Title