Serial Lite IV Intel® Stratix™ 10 FPGA IP Design Example User Guide

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ID 683223
Date 11/01/2021
Public
Document Table of Contents
Document Table of Contents x
1. About the Serial Lite IV Intel® Stratix® 10 FPGA IP Design Example User Guide 2. Quick Start Guide 3. Detailed Description for Serial Lite IV Design Example 4. Serial Lite IV Intel® Stratix® 10 FPGA IP Design Example User Guide Archives 5. Document Revision History for the Serial Lite IV Intel® Stratix® 10 FPGA IP Design Example User Guide
2. Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Compiling and Simulating the Design 2.5. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for Serial Lite IV Design Example x
3.1. Features 3.2. Design Example Components 3.3. Simulation 3.4. Hardware Testing 3.5. Error Handling 3.6. Link Debugging Sequence 3.7. Serial Lite IV IP Toolkit
3.2. Design Example Components x
3.2.1. Traffic Generator 3.2.2. Traffic Checker 3.2.3. DCFIFO 3.2.4. System Console 3.2.5. Demo Management 3.2.6. Demo Control
3.3. Simulation x
3.3.1. Simulation Results for Basic Mode 3.3.2. Simulation Result for Full Mode
3.4. Hardware Testing x
3.4.1. Hardware Testing Result for Basic Transfer Mode 3.4.2. Hardware Testing Result for Full Transfer Mode 3.4.3. Traffic Statistic Results
3.7. Serial Lite IV IP Toolkit x
3.7.1. Setting Up and Running the Toolkit 3.7.2. Toolkit GUI Settings
1. About the Serial Lite IV Intel® Stratix® 10 FPGA IP Design Example User Guide
2. Quick Start Guide
3. Detailed Description for Serial Lite IV Design Example
4. Serial Lite IV Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
5. Document Revision History for the Serial Lite IV Intel® Stratix® 10 FPGA IP Design Example User Guide

3.7.1. Setting Up and Running the Toolkit

To enable the Serial Lite IV IP toolkit, you must download and run the toolkit.
To run the toolkit, follow these steps:
  1. Generate the design example after you specify the parameters.
  2. Compile the design example to generate a .sof file.
  3. In the Intel® Quartus® Prime Pro Edition software, select Tools > System Debugging Tools > System Console to launch the system console.
  4. Based on the directory where your design example is generated, use the TCL command in the system console to set the current directory in the system console to ../ed_hwtest/sl4_ip_toolkit.
  5. Then, type the following command in the TCL console window.
    toolkit_register <full path directory>/sl4_ip_toolkit.toolkit.
  6. In the system console, go to Tools > Legacy Toolkits > Serial Lite IV IP Toolkit to launch the toolkit.
    Figure 19. Launch the Serial Lite IV IP Toolkit
When the toolkit is up and running, set JTAG master by following the instructions given in the display window.
Figure 20. Setting JTAG Master
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