Serial Lite IV Intel® Stratix™ 10 FPGA IP Design Example User Guide

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ID 683223
Date 11/01/2021
Public
Document Table of Contents
Document Table of Contents x
1. About the Serial Lite IV Intel® Stratix® 10 FPGA IP Design Example User Guide 2. Quick Start Guide 3. Detailed Description for Serial Lite IV Design Example 4. Serial Lite IV Intel® Stratix® 10 FPGA IP Design Example User Guide Archives 5. Document Revision History for the Serial Lite IV Intel® Stratix® 10 FPGA IP Design Example User Guide
2. Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Compiling and Simulating the Design 2.5. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for Serial Lite IV Design Example x
3.1. Features 3.2. Design Example Components 3.3. Simulation 3.4. Hardware Testing 3.5. Error Handling 3.6. Link Debugging Sequence 3.7. Serial Lite IV IP Toolkit
3.2. Design Example Components x
3.2.1. Traffic Generator 3.2.2. Traffic Checker 3.2.3. DCFIFO 3.2.4. System Console 3.2.5. Demo Management 3.2.6. Demo Control
3.3. Simulation x
3.3.1. Simulation Results for Basic Mode 3.3.2. Simulation Result for Full Mode
3.4. Hardware Testing x
3.4.1. Hardware Testing Result for Basic Transfer Mode 3.4.2. Hardware Testing Result for Full Transfer Mode 3.4.3. Traffic Statistic Results
3.7. Serial Lite IV IP Toolkit x
3.7.1. Setting Up and Running the Toolkit 3.7.2. Toolkit GUI Settings
1. About the Serial Lite IV Intel® Stratix® 10 FPGA IP Design Example User Guide
2. Quick Start Guide
3. Detailed Description for Serial Lite IV Design Example
4. Serial Lite IV Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
5. Document Revision History for the Serial Lite IV Intel® Stratix® 10 FPGA IP Design Example User Guide

3.4. Hardware Testing

The hardware design example provides two test methods; the loopback test mode and the master and slave test mode. For loopback test mode, the traffic generator sends packets to the Serial Lite IV TX core and loopback to the RX core either internally or externally. For the master and slave test mode, you need to set up two separate development kits; a master development kit to generate and verify packets and a slave development kit to receive and transfer packets back to the master.

Figure 10. Loopback Test Mode
Figure 11. Master and Slave Test Mode

You can test the design example using the system console.

Note: The design example targets the Intel® Stratix® 10 TX Transceiver Signal Integrity Development Kit . The design includes an .sdc script as well as a .qsf file with verified constraints in loopback mode. If you use the design example with another device or development board, you may need to update the device setting and constraints in the .qsf file.

To use the system console script, navigate to the ./ed_hwtest/system_console directory. Source the sliv_etile.tcl script. The system console script provides useful commands for reading statistics and enables you to control various features in the design.

Table 10.  System Console Commands for Hardware Testing
Command Function
list_jtag Displays a list of JTAG master indexes that are connected to your board.
set_jtag <jtag master_index number> Selects the JTAG master.
  • To enable internal and external loopback, use the JTAG master index number of phy_1/phy_jtag_m JTAG node.
    For example, the JTAG master index of phy_1/phy_jtag_m JTAG node shown in the following JTAG list is 2. Type set_jtag 2 to select JTAG master index 2. Next type the enable internal or external loopback commands. 
    % list_jtag
Available JTAG Masters:
0:    /devices/<JTAG_port>/phy_0/master
1:    /devices/<JTAG_port>/phy_0/demo_jtag_m.master
2:    /device/<JTAG_port>/phy_1/phy_jtag_m.master
  • To perform commands other than internal and external loopback, use JTAG master index number of phy_0/demo_jtag_m JTAG node.
    For example, the JTAG master index of phy_0/demo_jtag_m JTAG node shown in the following JTAG list is 1. Type set_jtag 1 to select JTAG master index 1. Next type the system console command that you want to use. 
    % list_jtag
Available JTAG Masters:
0:    /devices/<JTAG_port>/phy_0/master
1:    /devices/<JTAG_port>/phy_0/demo_jtag_m.master
2:    /device/<JTAG_port>/phy_1/phy_jtag_m.master
Note: After programming the .sof file, perform either sl4_link_init_int_lpbk or sl4_link_init_ext_lpbk before running the design example for proper transceiver calibration.
sl4_link_init_int_lpbk Enables TX to RX internal serial loopback within the transceiver and performs the specific transceiver calibration flow.
sl4_link_init_ext_lpbk Enables TX to RX external loopback and performs the specific transceiver calibration flow.
traffic_gen_enable Enables the traffic generator and checker.

The hardware design example runs in basic or pure streaming mode by default when the traffic generator is enabled.

traffic_gen_disable Disables the traffic generator and checker.
tx_source_traffic_reset Resets the TX datapath for the DCFIFO and traffic generator.
rx_sink_traffic_reset Resets the RX datapath for the DCFIFO and traffic checker.
read_error_statistic Displays the error statistics.
continuous_mode_en Resets the TX and RX core (MAC and PHY) and enables the traffic generator to generate continuous (single continuous data generation) traffic stream.
burst_mode_en Resets the TX and RX core (MAC and PHY) and enables the traffic generator to generate a burst (multiple burst packet data generation) traffic stream.
crc_err_inject_pulse Enables CRC error injection for all lanes.
slave_test_mode_enable This option disables the traffic generator/checker and enables the traffic to flow from sink to source. This option is only available for hardware setup with master and slave configuration using two different development kits.
slave_test_mode_disable This option disables data flow from sink to source. Select option 1 to enable the data generator and data checker.

In addition to this command script, you can also use the Serial Lite IV IP toolkit for real-time troubleshooting during active link operation.

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