Serial Lite IV Intel® Stratix™ 10 FPGA IP Design Example User Guide

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ID 683223
Date 11/01/2021
Public
Document Table of Contents
Document Table of Contents x
1. About the Serial Lite IV Intel® Stratix® 10 FPGA IP Design Example User Guide 2. Quick Start Guide 3. Detailed Description for Serial Lite IV Design Example 4. Serial Lite IV Intel® Stratix® 10 FPGA IP Design Example User Guide Archives 5. Document Revision History for the Serial Lite IV Intel® Stratix® 10 FPGA IP Design Example User Guide
2. Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Compiling and Simulating the Design 2.5. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for Serial Lite IV Design Example x
3.1. Features 3.2. Design Example Components 3.3. Simulation 3.4. Hardware Testing 3.5. Error Handling 3.6. Link Debugging Sequence 3.7. Serial Lite IV IP Toolkit
3.2. Design Example Components x
3.2.1. Traffic Generator 3.2.2. Traffic Checker 3.2.3. DCFIFO 3.2.4. System Console 3.2.5. Demo Management 3.2.6. Demo Control
3.3. Simulation x
3.3.1. Simulation Results for Basic Mode 3.3.2. Simulation Result for Full Mode
3.4. Hardware Testing x
3.4.1. Hardware Testing Result for Basic Transfer Mode 3.4.2. Hardware Testing Result for Full Transfer Mode 3.4.3. Traffic Statistic Results
3.7. Serial Lite IV IP Toolkit x
3.7.1. Setting Up and Running the Toolkit 3.7.2. Toolkit GUI Settings
1. About the Serial Lite IV Intel® Stratix® 10 FPGA IP Design Example User Guide
2. Quick Start Guide
3. Detailed Description for Serial Lite IV Design Example
4. Serial Lite IV Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
5. Document Revision History for the Serial Lite IV Intel® Stratix® 10 FPGA IP Design Example User Guide

2.1. Design Example Block Diagram

Figure 2. High-level Block Diagram for Intel® Stratix® 10 Design Examples
Table 3.  Design Example Components
Component Description
Serial Lite IV IP
The Serial Lite IV IP in this design example supports streaming or packet transfer mode with the following features:
  • 56 Gbps per lane with a maximum of eight PAM4 lanes with RS-FEC
  • 28 Gbps per lane with a maximum of 16 NRZ lanes with or without RS-FEC

The Serial Lite IV IP accepts data from the traffic generator and formats the data for transmission.

The Serial Lite IV IP also receives data from the link, strips the headers, and sends it to the traffic checker for analysis.

You generate the IP using the parameter editor in the Intel® Quartus® Prime Pro Edition software.

System Console

The System Console is an Intel® Quartus® Prime tool that provides a user-friendly interface for you to do first-level debugging and monitor the status of the IP, and the traffic generator, and checker.

Demo control The demo control module consists of Avalon® memory-mapped pipeline bridges connected to the transceiver reconfiguration and the demo management interfaces. The design also instantiates the JTAG master, parallel input/output (PIO), and ISSP (In-system Source and Probe) modules for System Console debugging purposes.
Demo management

The demo management module implements control and status registers (CSRs) to control, monitor the design operation, and log errors that occur during the operation.

User clock—IOPLL

For Intel® Stratix® 10 E-tile devices, the design example uses an IOPLL to generate a user clock to transmit data to the Serial Lite IV IP.

The design uses the iopll_ref_clk clock signal as an IOPLL reference clock to connect to the clock generator.

Important: The iopll_ref_clk should have the same frequency as the pll_refclk and come from the same clock module.
User clock—Transceiver reference clock

For Intel® Stratix® 10 E-tile devices, the design example uses a transceiver reference clock (xcvr_ref_clk_1) to preserve unused transceiver channels. This clock is only available in PAM4 mode when you turn on Preserve unused transceiver channels for PAM4 in the IP parameter editor. In NRZ mode, this clock is available by default.

Note: The xcvr_ref_clk_1 is driven to the frequency that you defined in Reference clock of preserved channels in the IP parameter editor.
Traffic generator

The traffic generator generates traffic in a deterministic format to verify that the link transmits data correctly.
Traffic checker

The traffic checker performs inspections to verify that the received data is in the expected format.
Dual-clock FIFO (DCFIFO)

The DCFIFO blocks handle data streaming and control signals for clock crossing between different clock domains.
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