Serial Lite IV Intel® Stratix™ 10 FPGA IP Design Example User Guide

Download PDF
ID 683223
Date 11/01/2021
Public
Document Table of Contents
Document Table of Contents x
1. About the Serial Lite IV Intel® Stratix® 10 FPGA IP Design Example User Guide 2. Quick Start Guide 3. Detailed Description for Serial Lite IV Design Example 4. Serial Lite IV Intel® Stratix® 10 FPGA IP Design Example User Guide Archives 5. Document Revision History for the Serial Lite IV Intel® Stratix® 10 FPGA IP Design Example User Guide
2. Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Compiling and Simulating the Design 2.5. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for Serial Lite IV Design Example x
3.1. Features 3.2. Design Example Components 3.3. Simulation 3.4. Hardware Testing 3.5. Error Handling 3.6. Link Debugging Sequence 3.7. Serial Lite IV IP Toolkit
3.2. Design Example Components x
3.2.1. Traffic Generator 3.2.2. Traffic Checker 3.2.3. DCFIFO 3.2.4. System Console 3.2.5. Demo Management 3.2.6. Demo Control
3.3. Simulation x
3.3.1. Simulation Results for Basic Mode 3.3.2. Simulation Result for Full Mode
3.4. Hardware Testing x
3.4.1. Hardware Testing Result for Basic Transfer Mode 3.4.2. Hardware Testing Result for Full Transfer Mode 3.4.3. Traffic Statistic Results
3.7. Serial Lite IV IP Toolkit x
3.7.1. Setting Up and Running the Toolkit 3.7.2. Toolkit GUI Settings
1. About the Serial Lite IV Intel® Stratix® 10 FPGA IP Design Example User Guide
2. Quick Start Guide
3. Detailed Description for Serial Lite IV Design Example
4. Serial Lite IV Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
5. Document Revision History for the Serial Lite IV Intel® Stratix® 10 FPGA IP Design Example User Guide

1. About the Serial Lite IV Intel® Stratix® 10 FPGA IP Design Example User Guide

Updated for:
Intel® Quartus® Prime Design Suite 21.3
IP Version 1.3.1

This document describes features, usage guidelines, and functional description of the Serial Lite IV Intel® FPGA IP design examples using E-tile transceivers in Intel® Stratix® 10 devices.

Intended Audience

This document is intended for the following users:
  • Design architects to make IP selection during system level design planning phase.
  • Hardware designers when integrating the IP into their system level design.
  • Validation engineers during system level simulation and hardware validation phase.

Related Documents

The following table lists other reference documents that are related to the Serial Lite IV Intel® FPGA IP.
Table 1.  Related Documents
Reference Description
Serial Lite IV Intel® FPGA IP User Guide

This user guide provides IP features, architecture description, steps to generate, and guidelines to design the Serial Lite IV Intel® FPGA IP using the E-tile transceivers.

Serial Lite IV Intel® Agilex™ Design Example User Guide This document provides features, usage guidelines, and functional description of the Serial Lite IV Intel® FPGA IP design examples in Intel® Agilex™ devices.
E-tile Hard IP User Guide: E-tile Hard IP for Ethernet and E-Tile CPRI PHY Intel FPGA IPs

This document describes the features, functionality, and guidelines of the E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IP cores in Intel® Stratix® 10 and Intel® Agilex™ devices.

Intel® Stratix® 10 Device Data Sheet

This document describes the electrical characteristics, switching characteristics, configuration specifications, and timing for Intel® Stratix® 10 devices.

E-Tile Transceiver PHY User Guide

This document describes the features, functionality, and guidelines of the E-Tile Transceiver PHY in Intel® Stratix® 10 and Intel® Agilex™ devices.

Intel® Stratix® 10 TX Transceiver Signal Integrity Development Kit User Guide

This document describes the features, functionality, and guidelines for the Intel® Stratix® 10 GX Transceiver Signal Integrity Development Kit.

Serial Lite IV Intel® FPGA IP Release Notes

This document lists the changes made in the IP for a particular release.

Acronyms and Glossary

Table 2.  Acronym List
Acronym Expansion
CW Control Word
RS-FEC Reed-Solomon Forward Error Correction
PMA Physical Medium Attachment
TX Transmitter
RX Receiver
PAM4 Pulse-Amplitude Modulation 4-Level
NRZ Non-return-to-zero
PCS Physical Coding Sublayer
MII Media Independent Interface
XGMII 10 Gigabit Media Independent Interface
Level Two Title