AN-731: Simultaneous Switching Noise Guidelines for Intel® Cyclone® 10 LP, Cyclone® IV, and Cyclone® III Devices

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ID 683204
Date 11/06/2017
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Simultaneous Switching Noise Guidelines for Intel® Cyclone® 10 LP, Cyclone® IV, and Cyclone® III Devices
Simultaneous Switching Noise Guidelines for Intel® Cyclone® 10 LP, Cyclone® IV, and Cyclone® III Devices x
External Clock Inputs Guidelines I/O Restriction Guidelines Single-Ended Clock Input Pad Placement Guideline Document Revision History for AN-731: Simultaneous Switching Noise Guidelines for Intel® Cyclone® 10 LP, Cyclone® IV, and Cyclone® III Devices
External Clock Inputs Guidelines x
Victim Clock Pin Assignments External Single-Ended Clock Input SSN Requirements Effects of I/O Termination Effect of Slow Aggressor Signal Slew Rate on SSN Effect of Fast Slew Rate of Victim Clock on SSN
Simultaneous Switching Noise Guidelines for Intel® Cyclone® 10 LP, Cyclone® IV, and Cyclone® III Devices

Single-Ended Clock Input Pad Placement Guideline

  • You can put two single-ended clocks on any of the four dedicated pins.
    • Asynchronous input or output signals are not allowed on the two left most and right most pins.
  • If you want to put three or four single-ended clocks on the four dedicated pins.
    • Check mutual inductance of these pins
    • Contact Intel FPGA mySupport if you cannot correlate the pad location and mutual inductance
  • To avoid crosstalk, do not put the aggressor pin adjacent to the victim clock input pin.
    • Separate the aggressor pin and the victim pin by two or more pins
    • You can check the separation in Intel® Quartus® Prime Pad Viewer
Figure 7. Single-Ended Clock Input Pad Placement GuidelineSingle-ended input or output signals are not allowed on the two left-most and right-most pins to provide a single-ended clock input on the general-purpose pins.
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