AN-731: Simultaneous Switching Noise Guidelines for Intel® Cyclone® 10 LP, Cyclone® IV, and Cyclone® III Devices

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ID 683204
Date 11/06/2017
Public
Document Table of Contents
Document Table of Contents x
Simultaneous Switching Noise Guidelines for Intel® Cyclone® 10 LP, Cyclone® IV, and Cyclone® III Devices
Simultaneous Switching Noise Guidelines for Intel® Cyclone® 10 LP, Cyclone® IV, and Cyclone® III Devices x
External Clock Inputs Guidelines I/O Restriction Guidelines Single-Ended Clock Input Pad Placement Guideline Document Revision History for AN-731: Simultaneous Switching Noise Guidelines for Intel® Cyclone® 10 LP, Cyclone® IV, and Cyclone® III Devices
External Clock Inputs Guidelines x
Victim Clock Pin Assignments External Single-Ended Clock Input SSN Requirements Effects of I/O Termination Effect of Slow Aggressor Signal Slew Rate on SSN Effect of Fast Slew Rate of Victim Clock on SSN
Simultaneous Switching Noise Guidelines for Intel® Cyclone® 10 LP, Cyclone® IV, and Cyclone® III Devices

Document Revision History for AN-731: Simultaneous Switching Noise Guidelines for Intel® Cyclone® 10 LP, Cyclone® IV, and Cyclone® III Devices

Date Version Changes
November 2017 2017.11.06
  • Added Intel® Cyclone® 10 LP support.
  • Made editorial text and structure update.
  • Rebranded as Intel.
  • Retitle the document.
February 2015 2015.02.04 Initial release.
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