AN-731: Simultaneous Switching Noise Guidelines for Intel® Cyclone® 10 LP, Cyclone® IV, and Cyclone® III Devices

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ID 683204
Date 11/06/2017
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Document Table of Contents x
Simultaneous Switching Noise Guidelines for Intel® Cyclone® 10 LP, Cyclone® IV, and Cyclone® III Devices
Simultaneous Switching Noise Guidelines for Intel® Cyclone® 10 LP, Cyclone® IV, and Cyclone® III Devices x
External Clock Inputs Guidelines I/O Restriction Guidelines Single-Ended Clock Input Pad Placement Guideline Document Revision History for AN-731: Simultaneous Switching Noise Guidelines for Intel® Cyclone® 10 LP, Cyclone® IV, and Cyclone® III Devices
External Clock Inputs Guidelines x
Victim Clock Pin Assignments External Single-Ended Clock Input SSN Requirements Effects of I/O Termination Effect of Slow Aggressor Signal Slew Rate on SSN Effect of Fast Slew Rate of Victim Clock on SSN
Simultaneous Switching Noise Guidelines for Intel® Cyclone® 10 LP, Cyclone® IV, and Cyclone® III Devices

I/O Restriction Guidelines

To reduce the impact of SSN due to potential aggressor signals, I/O restrictions are essential to control the number of toggling aggressor signals in the same I/O bank.

Table 1.  I/O Restriction Guidelines per BankThis table lists the percentages of the total number of I/O pins that can be toggled without inducing any error on the victim single-ended clock under SSN and/or crosstalk condition. The numbers in the table are based on actual measurements that were done using an Intel characterization system setup. These measurements may vary based on your system design and the board configuration. As shown in the table, crosstalk is the primary cause of attenuation or malfunction of the victim clock input.
Aggressor I/O Standards Percentage of Simultaneous Switching Pins per Bank
4-Layer Wire-bonding Package 2-Layer Wire-bonding Package
Forward toggling pattern Reverse toggling pattern Forward toggling pattern Reverse toggling pattern

3.0V LVCMOS 16mA (fast slew rate)

13%

95%

5%

5%

2.5V LVTTL 16mA (fast slew rate)

55%

95%

27%

84%

2.5V LVTTL 12mA (fast slew rate)

55%

96%

27%

84%

2.5V LVTTL 4mA

100%

100%

100%

100%

2.5V SSTL 2.5V Class II 16mA (fast slew rate)

100%

100%

100%

100%

The following tests are performed to better understand crosstalk and the effect of power and/or ground noise on the victim clock inputs:

  • Forward toggling pattern test—in this test each aggressor, starting from the closest to the farthest from the victim is switched on one by one, until an error occurs. The main influence of crosstalk on the victim clock input is measured, and the number of switched-on aggressors are noted.
  • Reverse toggling pattern test—in this test each aggressor, starting from the farthest to the closest from the victim, is switched on one by one, until an error occurs. The primary influence of power and ground noise on the victim clock input is measured, and the number of switched-on aggressors are noted.

Reverse toggling pattern test confirms that a 2-layer substrate package is more susceptible to SSN than a 4-layer substrate package.

It is difficult to quantify the effect of SSN and crosstalk on the victim clock input separately.

You can prevent the PLL unlock issue or counter malfunction by using the potential aggressor signals with lower current strength and terminated I/O standard.

Level Two Title