AN-731: Simultaneous Switching Noise Guidelines for Intel® Cyclone® 10 LP, Cyclone® IV, and Cyclone® III Devices

Download PDF
ID 683204
Date 11/06/2017
Public
Document Table of Contents
Document Table of Contents x
Simultaneous Switching Noise Guidelines for Intel® Cyclone® 10 LP, Cyclone® IV, and Cyclone® III Devices
Simultaneous Switching Noise Guidelines for Intel® Cyclone® 10 LP, Cyclone® IV, and Cyclone® III Devices x
External Clock Inputs Guidelines I/O Restriction Guidelines Single-Ended Clock Input Pad Placement Guideline Document Revision History for AN-731: Simultaneous Switching Noise Guidelines for Intel® Cyclone® 10 LP, Cyclone® IV, and Cyclone® III Devices
External Clock Inputs Guidelines x
Victim Clock Pin Assignments External Single-Ended Clock Input SSN Requirements Effects of I/O Termination Effect of Slow Aggressor Signal Slew Rate on SSN Effect of Fast Slew Rate of Victim Clock on SSN
Simultaneous Switching Noise Guidelines for Intel® Cyclone® 10 LP, Cyclone® IV, and Cyclone® III Devices

Effect of Slow Aggressor Signal Slew Rate on SSN

Crosstalk is inversely proportional to rise time. There is an increase in crosstalk when the aggressor signal has fast rise and fall time.
Equation 1. Crosstalk Equation

To decrease SSN caused by crosstalk, use the slowest slew rate for potential aggressor signals, especially when multiple I/O signals are switching simultaneously.

Figure 5. Crosstalk MechanismThis figure shows an example of a victim signal that is degraded by crosstalk


Level Two Title