Board Management Controller User Guide: Intel FPGA Programmable Acceleration Card N3000-N

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ID 683186
Date 9/08/2020
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Board Monitoring through PLDM over MCTP SMBus 3. Board Monitoring through I2C SMBus 4. EEPROM Data Format 5. Document Revision History for Board Management Controller User Guide: Intel FPGA Programmable Acceleration Card N3000-N A. Example PLDM Command and Response Messages
1. Introduction x
1.1. About this Document 1.2. Overview 1.3. Root of Trust (RoT) 1.4. Secure Remote System Update 1.5. Power Sequence Management 1.6. Board Monitoring Through Sensors
2. Board Monitoring through PLDM over MCTP SMBus x
2.1. SMBus Interface Speed 2.2. MCTP Packetization Support 2.3. Supported Command Sets 2.4. PLDM Topology and Hierarchy
4. EEPROM Data Format x
4.1. MAC EEPROM 4.2. Field Replaceable Unit Identification (FRUID) EEPROM Access
1. Introduction
2. Board Monitoring through PLDM over MCTP SMBus
3. Board Monitoring through I2C SMBus
4. EEPROM Data Format
5. Document Revision History for Board Management Controller User Guide: Intel FPGA Programmable Acceleration Card N3000-N
A. Example PLDM Command and Response Messages

2.4. PLDM Topology and Hierarchy

Defined Platform Descriptor Records

The Intel® FPGA PAC N3000-N uses 20 Platform Descriptor Records (PDRs). Intel® MAX® 10 BMC only supports consolidated PDRs where the PDRs will not be added or removed dynamically when QSFP is plugged and unplugged. When unplugged the sensor operational status will simply be reported as unavailable.

Sensor Names and Record Handle

All PDRs are assigned an opaque numeric value called the Record Handle. This value is used for accessing individual PDRs within the PDR Repository via GetPDR (DTMF specification DSP0248).

The following table is a consolidated list of sensors monitored on Intel® FPGA PAC N3000-N.

Table 1.  PDRs Sensor Names and Record HandlePlease refer to Intel FPGA Programmable Acceleration Card N3000-N ReadMe for sensor output information.
Function Sensor Name Sensor Information PLDM
Sensor Reading Source (Component) PDR Record Handle Thresholds in PDR Threshold changes allowed via PLDM
Total Intel® FPGA PAC input power Board Power Calculated using the formula:

(12 V Backplace Current * 12 V Backplane Voltage) + (12 V Aux Current * 12 V Aux Voltage)

1 0 No
PCIe* fingers 12 V Current 12 V Backplane Current PAC1932 SENSE1 2 0 No
PCIe* fingers 12 V Voltage 12 V Backplane Voltage PAC1932 SENSE1 3 0 No
1.2 V Rail Voltage 1.2 V Voltage MAX10 ADC 4 0 No
1.8 V Rail Voltage 1.8 V Voltage MAX 10 ADC 6 0 No
3.3 V Rail Voltage 3.3 V Voltage MAX 10 ADC 8 0 No
FPGA Core Voltage FPGA Core Voltage LTC3884 10 0 No
FPGA Core Current FPGA Core Current LTC3884 11 0 No
FPGA Core Temperature FPGA Core Temperature FPGA temp diode via TMP411 12
  • Upper Warning: 90
  • Upper Fatal: 100
 Yes
Board Temperature Board Temperature TMP411 13
  • Upper Warning: 85
  • Upper Fatal: 100
 Yes
QSFP A Voltage QSFP A Voltage

External QSFP module

14 0 No
QSFP A Temperature QSFP A Temperature

External QSFP module

 15
  • Upper Warning: Value set by QSFP Vendor
  • Upper Fatal: Value set by QSFP Vendor
 No
PCIe Auxiliary 12V Current 12 V AUX Current PAC1932 SENSE2 24 0 No
PCIe Auxiliary 12V Voltage 12 V AUX Voltage PAC1932 SENSE2 25 0 No
QSFP B Voltage QSFP B Voltage

External QSFP module

37 0 No
QSFP B Temperature QSFP B Temperature

External QSFP module

38
  • Upper Warning: Value set by QSFP Vendor
  • Upper Fatal: Value set by QSFP Vendor
 No
Intel C827 Retimer A Core Temperature Retimer A Core Temperature Intel C827 Retimer chip (88EC055) (U18A) 44 0 No
Intel C827 Retimer A Serdes Temperature Retimer A Serdes Temperature Intel C827 Retimer chip (88EC055) (U18A) 45 0 No
Intel C827 Retimer B Core Temperature Retimer B Core Temperature Intel C827 Retimer chip (88EC055) (U23A) 46 0 No
Intel C827 Retimer B Serdes Temperature Retimer B Serdes Temperature Intel C827 Retimer chip (88EC055) (U23A) 47 0 No
Note: The Upper Warning and Upper Fatal values for QSFP are set by the QSFP vendor. Refer to vendor datasheet for the values. The BMC reads these threshold values and reports them out.
Note: If a sensor status shows as unavailable, please check if the card is still operational and not shut down due to over-heating. The LEDS blink yellow in case of card shut down. In such scenario restart the server and provide sufficient cooling to the card to keep it operational and read the sensor data. Refer to the Cooling Requirements section in the Intel FPGA Programmable Acceleration Card N3000-N Data Sheet.

Please refer to Appendix A: Example PLDM Command and Response Messages for an example PLDM command to read the board temperature.

fpgad is a service that can help you protect the server from crashing when the hardware reaches an upper non-recoverable or lower non-recoverable sensor threshold (also called as fatal threshold).

fpgad is capable of monitoring each of the 20 sensors reported by the Board Management Controller.

Please refer to the Graceful Shutdown topic from Intel Acceleration Stack User Guide: Intel FPGA Programmable Acceleration Card N3000-N for more information.

You can obtain the values of the sensors by running the following OPAE command as root or sudo: 
$ sudo fpgainfo bmc
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