Board Management Controller User Guide: Intel FPGA Programmable Acceleration Card N3000-N

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ID 683186
Date 9/08/2020
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Board Monitoring through PLDM over MCTP SMBus 3. Board Monitoring through I2C SMBus 4. EEPROM Data Format 5. Document Revision History for Board Management Controller User Guide: Intel FPGA Programmable Acceleration Card N3000-N A. Example PLDM Command and Response Messages
1. Introduction x
1.1. About this Document 1.2. Overview 1.3. Root of Trust (RoT) 1.4. Secure Remote System Update 1.5. Power Sequence Management 1.6. Board Monitoring Through Sensors
2. Board Monitoring through PLDM over MCTP SMBus x
2.1. SMBus Interface Speed 2.2. MCTP Packetization Support 2.3. Supported Command Sets 2.4. PLDM Topology and Hierarchy
4. EEPROM Data Format x
4.1. MAC EEPROM 4.2. Field Replaceable Unit Identification (FRUID) EEPROM Access
1. Introduction
2. Board Monitoring through PLDM over MCTP SMBus
3. Board Monitoring through I2C SMBus
4. EEPROM Data Format
5. Document Revision History for Board Management Controller User Guide: Intel FPGA Programmable Acceleration Card N3000-N
A. Example PLDM Command and Response Messages

1.2. Overview

The Intel® MAX® 10 BMC is responsible for controlling, monitoring and granting access to board features. The Intel® MAX® 10 BMC interfaces with on-board sensors, the FPGA and the flash, and manages power-on/power-off sequences, FPGA configuration and telemetry data polling. You can communicate with the BMC using the PLDM version 1.1.1 protocol. The BMC firmware is field upgradeable over PCIe using the remote system update feature.

Features of BMC

  • Acts as a Root of Trust (RoT) and enables the secure update features of the Intel® FPGA PAC N3000-N.
  • Controls firmware and FPGA flash updates over PCIe.
  • Manages FPGA configuration.
  • Updates the C827 Ethernet Retimer device firmware.
  • Controls power sequencing and fault detection with automatic shut-down protection.
  • Controls power and resets on the board.
  • Interfaces with sensors, FPGA flash and QSFPs.
  • Monitors telemetry data (board temperature, voltage, and current) and provides protective action when readings are beyond the critical threshold.
    • Reports telemetry data to host BMC via PLDM over MCTP via SMBus or through I2C.
    • Supports PLDM over MCTP via PCIe SMBus. 0xCE is the 8-bit slave address.
    • Supports I2C. 0xBC is the 8-bit slave address.
  • Accesses the EEPROM containing the Ethernet MAC address of the Intel® Ethernet Controller XL710-BM2.
Figure 1. Block Diagram
Level Two Title