AN 909: JESD204C Intel® FPGA IP and TI ADC12DJ5200RF Interoperability Report for Intel® Stratix® 10 Devices

Download PDF
ID 683185
Date 6/09/2020
Public
Document Table of Contents
Document Table of Contents x
1. JESD204C Intel® FPGA IP and TI ADC12DJ5200RF Interoperability Report for Intel® Stratix® 10 Devices
1. JESD204C Intel® FPGA IP and TI ADC12DJ5200RF Interoperability Report for Intel® Stratix® 10 Devices x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. ADC12DJxx00RF EVM Software and JESD204C Example Design Setup 1.4. Hardware Checkout Methodology 1.5. JESD204C Intel® FPGA IP and ADC Configurations 1.6. Test Results 1.7. Test Result Comments 1.8. Document Revision History for AN 909: JESD204C Intel® FPGA IP and TI ADC12DJ5200RF Interoperability Report for Intel® Stratix® 10 Devices 1.9. Appendix
1.4. Hardware Checkout Methodology x
1.4.1. Receiver Data Link Layer 1.4.2. Receiver Transport Layer 1.4.3. Deterministic Latency (Subclass 1)
1.4.1. Receiver Data Link Layer x
1.4.1.1. Sync Header Alignment 1.4.1.2. Extended Multiblock Alignment
1. JESD204C Intel® FPGA IP and TI ADC12DJ5200RF Interoperability Report for Intel® Stratix® 10 Devices

1.5. JESD204C Intel® FPGA IP and ADC Configurations

The JESD204C Intel® FPGA IP parameters (L, M, and F) in this hardware checkout are natively supported by the ADC12DJ5200RF device. The transceiver data rate, sampling clock, and other JESD204C parameters comply with the ADC12DJ5200RF operating conditions.

The hardware checkout testing implements the JESD204C Intel® FPGA IP with the following parameter configuration

Global setting for all configuration:
  • E = 1
  • CF = 0
  • Subclass = 1
  • SH_CONFIG = CRC-12
  • FCLK_MULP = 1
  • FPGA Management Clock (MHz) = 100
Note:
  • The other configurations are retained at default values.
  • The polarity of the DB0 to DB7 lanes of ADC12DJ5200RF EVM are inverted.
Table 5.  Parameter Configuration
LMF N NP S CS HD ADC Sampling Clock (MHz) FPGA Device Clock (MHz) 8 FPGA Frame / Link Clock (MHz) 9 Lane Rate (Gbps) DDC Enabled Decimation Factor Data Pattern
828 12 12 20 0 0 3000 150.00 75.00 9.9 No 1 Short
612 12 12 8 0 1 2500 156.25 78.125 10.3125 No 1 Short
622 12 12 4 0 1 2500 156.25 78.125 10.3125 No 1 Short
411 8 8 4 0 0 2500 156.25 78.125 10.3125 No 1 Short
421 8 8 2 0 0 2500 156.25 78.125 10.3125 No 1 Short
422 15 16 2 1 0 2500 156.25 78.125 10.3125 Yes 4 Long
442 15 16 1 1 0 2500 156.25 78.125 10.3125 Yes 4 Long
222 15 16 1 1 0 2500 156.25 78.125 10.3125 Yes 8 Long
244 15 16 1 1 0 2500 156.25 78.125 10.3125 Yes 8 Long
881 8 8 1 0 0 3000 150.00 75.00 9.9 No 1 Ramp
661 8 8 1 0 0 2500 156.25 78.125 10.3125 No 1 Ramp
828 12 12 20 0 0 5200 260.00 130.00 17.16 No 1 Short
612 12 12 8 0 1 4000 250.00 125.00 16.5 No 1 Short
622 12 12 4 0 1 4000 250.00 125.00 16.5 No 1 Short
411 8 8 4 0 0 4000 250.00 125.00 16.5 No 1 Short
421 8 8 2 0 0 4000 250.00 125.00 16.5 No 1 Short
422 15 16 2 1 0 4000 250.00 125.00 16.5 Yes 4 Long
442 15 16 1 1 0 4000 250.00 125.00 16.5 Yes 4 Long
222 15 16 1 1 0 4000 250.00 125.00 16.5 Yes 8 Long
244 15 16 1 1 0 4000 250.00 125.00 16.5 Yes 8 Long
881 8 8 1 0 0 5200 260.00 130.00 17.16 No 1 Ramp
661 8 8 1 0 0 4000 250.00 125.00 16.5 No 1 Ramp
8 The device clock is used to clock the E-tile transceiver as well as the core PLL of the JESD204C IP.
9 The frame clock and link clock are derived from the device clock using an internal Core PLL.
Level Two Title