AN 909: JESD204C Intel® FPGA IP and TI ADC12DJ5200RF Interoperability Report for Intel® Stratix® 10 Devices

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ID 683185
Date 6/09/2020
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1. JESD204C Intel® FPGA IP and TI ADC12DJ5200RF Interoperability Report for Intel® Stratix® 10 Devices
1. JESD204C Intel® FPGA IP and TI ADC12DJ5200RF Interoperability Report for Intel® Stratix® 10 Devices x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. ADC12DJxx00RF EVM Software and JESD204C Example Design Setup 1.4. Hardware Checkout Methodology 1.5. JESD204C Intel® FPGA IP and ADC Configurations 1.6. Test Results 1.7. Test Result Comments 1.8. Document Revision History for AN 909: JESD204C Intel® FPGA IP and TI ADC12DJ5200RF Interoperability Report for Intel® Stratix® 10 Devices 1.9. Appendix
1.4. Hardware Checkout Methodology x
1.4.1. Receiver Data Link Layer 1.4.2. Receiver Transport Layer 1.4.3. Deterministic Latency (Subclass 1)
1.4.1. Receiver Data Link Layer x
1.4.1.1. Sync Header Alignment 1.4.1.2. Extended Multiblock Alignment
1. JESD204C Intel® FPGA IP and TI ADC12DJ5200RF Interoperability Report for Intel® Stratix® 10 Devices

1.3. ADC12DJxx00RF EVM Software and JESD204C Example Design Setup

The ADC12DJxx00RF EVM software configures the ADC12DJ5200RF device, LMK61E2 programmable oscillator, LMK04828 clock generator, and LMX2594 frequency synthesizer for JESD204C link operation. Setup files for each parameter configuration are included in the software installation. You must configure the LMK61E2, LMK04828, LMX2594, and ADC12DJ5200RF modules with the correct settings and order, for the JESD204C link to operate at the targeted data rate and JESD204C link parameters.

Follow these steps to set up the configuration via the ADC12DJ5200RF EVM graphical user interface (GUI):

  1. Configure the clock modules by loading the configuration from Script→Load Config Script menu option in the GUI.
    Note: Use the Load Config Script option instead of the Program clocks and ADC option in GUI for configuring clock and ADC on ADC12DJ5200RF EVM to execute the test as per the flow defined below.
  2. Load the clock modules configuration scripts in the following order:
    1. LMK61E2_xxxM.cfg
    2. LMK04828_JMODE30_to_39.cfg
    3. LMX2594_xxxxM_xxxM.cfg
  3. Use the following configuration files for the lane rates specified:
    Lane Rate (Gbps) Configuration File (.cfg)
    9.9 LMK61E2_150M
    10.3125 LMK61E2_156p25M
    16.5 LMK61E2_250M
    17.6 LMK61E2_260M
  4. All supported lane rates and JESD204C 64B/66B modes of the ADC12DJ5200RF device uses LMK04828_JMODE30_to_39.cfg file. Use this file with the following modifications to provide SYSREF to SYSREFREQ pin of LMX2594:
    • 0x134 0x20 // Set SDCLKout13_MUX to SYSREF output & Bypass SDCLKout13 delay
    • 0x137 0x11 // Set SDCLKout13 output format to LVDS
  5. Use the following LMX2594 configuration files for the lane rates specified with the corresponding modifications to enable SYSREF REPEATER mode:
    Lane Rate (Gbps) Configuration File (.cfg) Modification
    9.9 LMKX2594_3000M_150M
    • 0x4B 0x0840 //[10:6]CHDIV
    • 0x49 0x06E4 //SYSREF Delay Control-Mi
    • 0x47 0x008D //[3]SYSREF_EN-1, [2]SYSREF_REPEAT-1
    • 0x3A 0x0001 //[15]SYSREFREQ Pin enable
    • 0x2E 0x07FE //[1:0]RFoutB MUX - SYSREF
    • 0x2C 0x1F23 //[7]RFoutB - Power UP
    • 0x25 0x0404 //[13:8]PFD_DLY_SEL
    • 0x24 0x0050 //PLL_N
    • 0x0C 0x5004 //PLL_R_PRE
    • 0x0B 0x0018 //[11:4]PLL_R
    • 0x04 0x0F43 //[15:8]ACAL_CMP_DLY
    • 0x01 0x0808 //CAL_CLK_DIV
    • 0x00 0x6418 //[14]VCO_PHASE_SYNC_EN - required for SYSREF_REPEAT
    10.3125 LMKX2594_2500M_156p25M
    • 0x4B 0x0840 //[10:6]CHDIV
    • 0x49 0x06E4 //SYSREF Delay Control-Min
    • 0x47 0x008D //[3]SYSREF_EN-1, [2]SYSREF_REPEAT-1
    • 0x3A 0x0001 //[15]SYSREFREQ Pin enable
    • 0x2E 0x07FE //[1:0]RFoutB MUX - SYSREF
    • 0x2C 0x1F23 //[7]RFoutB - Power UP
    • 0x25 0x0304 //[13:8]PFD_DLY_SEL
    • 0x24 0x0040 //PLL_N
    • 0x0C 0x5004 //PLL_R_PRE
    • 0x0B 0x0018 //[11:4]PLL_R
    • 0x04 0x1043 //[15:8]ACAL_CMP_DLY
    • 0x01 0x0808 //CAL_CLK_DIV
    • 0x00 0x6418 //[14]VCO_PHASE_SYNC_EN - required for SYSREF_REPEAT
    16.5 LMKX2594_4000M_250M
    • 0x4B 0x0800 //[10:6]CHDIV
    • 0x49 0x06E4 //SYSREF Delay Control-Min
    • 0x47 0x008D //[3]SYSREF_EN-1, [2]SYSREF_REPEAT-1
    • 0x3A 0x0001 //[15]SYSREFREQ Pin enable
    • 0x2E 0x07FE //[1:0]RFoutB MUX - SYSREF
    • 0x2C 0x1F23 //[7]RFoutB - Power UP
    • 0x25 0x0304 //[13:8]PFD_DLY_SEL
    • 0x24 0x0040 //PLL_N
    • 0x0C 0x5004 //PLL_R_PRE
    • 0x0B 0x0028 //[11:4]PLL_R
    • 0x04 0x0C43 //[15:8]ACAL_CMP_DLY
    • 0x01 0x0809 //CAL_CLK_DIV
    • 0x00 0x6418 //[14]VCO_PHASE_SYNC_EN - required for SYSREF_REPEAT
    17.16 LMKX2594_5200M_260M
    • 0x4B 0x0800 //[10:6]CHDIV
    • 0x49 0x06E4 //SYSREF Delay Control-Min
    • 0x47 0x008D //[3]SYSREF_EN-1, [2]SYSREF_REPEAT-1
    • 0x3A 0x0001 //[15]SYSREFREQ Pin enable
    • 0x2E 0x07FE //[1:0]RFoutB MUX - SYSREF
    • 0x2C 0x1F23 //[7]RFoutB - Power UP
    • 0x25 0x0404 //[13:8]PFD_DLY_SEL
    • 0x24 0x0028 //PLL_N
    • 0x0C 0x5004 //PLL_R_PRE
    • 0x0B 0x0018 //[11:4]PLL_R
    • 0x04 0x0D43 //[15:8]ACAL_CMP_DLY
    • 0x01 0x0809 //CAL_CLK_DIV
    • 0x00 0x6418 //[14]VCO_PHASE_SYNC_EN - required for SYSREF_REPEAT
  6. Configure the FPGA with the JESD204C Intel® FPGA IP example design by setting the PMA parameters GS1-2, GS2-2, RF-B0-3 and RF_B1-4, and SYSREF to use the external SYSREF from the FMC+ connector instead of the SYSREF from the SYSREF generator in the JESD204C Intel® FPGA IP example design.
  7. Configure the ADC12DJ5200RF device to the supported JESD204C link parameter by loading the configuration script from Script→Load Config Script menu option in the GUI.
  8. Use the following ADC12DJ5200RF device configuration files with the corresponding modifications for transport layer testing of the mode specified:
    LMF Configuration File (.cfg) Modification
    828 ADC12DJxx00RF_JMODE31
    • 0x0204 0x01 // Use SYNCSE input, offset binary data, scrambler enabled
    • 0x0205 0x05 // Transport Layer test mode
    • 0x0048 0x00 // Set serializer pre-emphasis to 0
    622 ADC12DJxx00RF_JMODE33
    411 ADC12DJxx00RF_JMODE34
    421 ADC12DJxx00RF_JMODE35
    422 ADC12DJxx00RF_JMODE36
    442 ADC12DJxx00RF_JMODE37
    222 ADC12DJxx00RF_JMODE38
    244 ADC12DJxx00RF_JMODE39
    881 ADC12DJxx00RF_JMODE30
    • 0x0204 0x01 // Use SYNCSE input, offset binary data, scrambler enabled
    • 0x0205 0x04 // Ramp test mode
    • 0x0048 0x00 // Set serializer pre-emphasis to 0
    661 ADC12DJxx00RF_JMODE32
  9. Use the following ADC12DJ5200RF device configuration files with the corresponding modifications for deterministic latency measurement of the mode specified:
    LMF Configuration File (.cfg) Modification
    828 ADC12DJxx00RF_JMODE31
    • 0x0061 0x00 // Clear CAL_EN (always after JESD_EN)
    • 0x0029 0x7x // Enable SYSREF Processing, SYSREF receiver circuit, SYSREF_ZOOM & [3:0]SYSREF_SEL (set based on section 7.3.6.3.1 of ADC12DJ5200RF data sheet)
    • 0x002A 0x02 // Enable SYSREF LVPECL
    • 0x002A 0x02 // Enable SYSREF LVPECL
    • 0x003B 0x03 // TMSTP_RECV_EN, TMSTP_LVPECL_EN
    • 0x0160 0x01 // TIME_STAMP_EN
    612 ADC12DJxx00RF_JMODE32
    622 ADC12DJxx00RF_JMODE33
    411 ADC12DJxx00RF_JMODE34
    421 ADC12DJxx00RF_JMODE35
    422 ADC12DJxx00RF_JMODE36
    442 ADC12DJxx00RF_JMODE37
    222 ADC12DJxx00RF_JMODE38
    244 ADC12DJxx00RF_JMODE39
    881 ADC12DJxx00RF_JMODE30
    • 0x002A 0x02 // Enable SYSREF LVPECL
    • 0x003B 0x03 // TMSTP_RECV_EN, TMSTP_LVPECL_EN
    • 0x0160 0x01 // TIME_STAMP_EN
    661 ADC12DJxx00RF_JMODE32
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