AN 909: JESD204C Intel® FPGA IP and TI ADC12DJ5200RF Interoperability Report for Intel® Stratix® 10 Devices

Download PDF
ID 683185
Date 6/09/2020
Public
Document Table of Contents
Document Table of Contents x
1. JESD204C Intel® FPGA IP and TI ADC12DJ5200RF Interoperability Report for Intel® Stratix® 10 Devices
1. JESD204C Intel® FPGA IP and TI ADC12DJ5200RF Interoperability Report for Intel® Stratix® 10 Devices x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. ADC12DJxx00RF EVM Software and JESD204C Example Design Setup 1.4. Hardware Checkout Methodology 1.5. JESD204C Intel® FPGA IP and ADC Configurations 1.6. Test Results 1.7. Test Result Comments 1.8. Document Revision History for AN 909: JESD204C Intel® FPGA IP and TI ADC12DJ5200RF Interoperability Report for Intel® Stratix® 10 Devices 1.9. Appendix
1.4. Hardware Checkout Methodology x
1.4.1. Receiver Data Link Layer 1.4.2. Receiver Transport Layer 1.4.3. Deterministic Latency (Subclass 1)
1.4.1. Receiver Data Link Layer x
1.4.1.1. Sync Header Alignment 1.4.1.2. Extended Multiblock Alignment
1. JESD204C Intel® FPGA IP and TI ADC12DJ5200RF Interoperability Report for Intel® Stratix® 10 Devices

1.9. Appendix

Intel® Quartus® Prime Pro Edition software version 19.2 Build 57 is used for compilation of designs.

This interoperability report refers to the April 2019 version of the ADC12DJ5200RF datasheet and EVM GUI.

Additional JESD mode support by ADC

The 64/66 B mode enlisted here have not been validated in this interoperability test, but they are supported by the ADC12DJ5200RF device. It is tabulated here for future reference.

LMF S N N' Comments
818 40 12 12 S=40 is not supported by JESD204C Intel® FPGA IP.
Level Two Title