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1. Acronyms
2. Introduction
3. IP Architecture and Functional Description
4. Advanced Features
5. Interfaces
6. Parameters
7. Testbench
8. Troubleshooting/Debugging
9. F-Tile Avalon Streaming Intel FPGA IP for PCI Express User Guide Archives
10. Revision History for the F-Tile Avalon Streaming Intel FPGA IP for PCI Express User Guide
A. Configuration Space Registers
B. Implementation of Address Translation Services (ATS) in Endpoint Mode
C. Packets Forwarded to the User Application in TLP Bypass Mode
D. Root Port Enumeration
E. Bifurcated Endpoint Support for Independent Resets
3.1. Architecture
3.2. Functional Description
3.3. Avalon-ST TX/RX
3.4. Interrupts
3.5. Completion Timeout
3.6. Hot Plug
3.7. Power Management
3.8. Configuration Output Interface (COI)
3.9. Configuration Intercept Interface (EP Only)
3.10. Hard IP Reconfiguration Interface
3.11. PHY Reconfiguration Interface
3.12. Page Request Service (PRS) (EP Only)
5.1. Overview
5.2. Clocks and Resets
5.3. Serial Data Interface
5.4. Avalon-ST Interface
5.5. Interrupt Interface
5.6. Hard IP Status Interface
5.7. Error Interface
5.8. 10-bit Tag Support Interface
5.9. Completion Timeout Interface
5.10. Power Management Interface
5.11. Hot Plug Interface (RP Only)
5.12. Configuration Output Interface
5.13. Configuration Intercept Interface (EP Only)
5.14. Hard IP Reconfiguration Interface
5.15. PHY Reconfiguration Interface
5.16. Page Request Service (PRS) Interface (EP Only)
5.17. FLR Interface Signals
5.18. PTM Interface Signals
5.19. VF Error Flag Interface Signals
5.20. VirtIO PCI Configuration Access Interface Signals
6.2.3.1. Device Capabilities
6.2.3.2. Link Capabilities
6.2.3.3. Legacy Interrupt Pin Register
6.2.3.4. MSI Capabilities
6.2.3.5. MSI-X Capabilities
6.2.3.6. Slot Capabilities
6.2.3.7. Latency Tolerance Reporting (LTR)
6.2.3.8. Process Address Space ID (PASID)
6.2.3.9. Device Serial Number Capability
6.2.3.10. Page Request Service (PRS)
6.2.3.11. Access Control Service (ACS) Capabilities
6.2.3.12. Power Management
6.2.3.13. Vendor Specific Extended Capability (VSEC) Registers
6.2.3.14. Precision Time Measurement (PTM)
6.2.3.15. Address Translation Services (ATS)
6.2.3.16. TLP Processing Hints (TPH)
6.2.3.17. VirtIO Parameters
7.6.1. ebfm_barwr Procedure
7.6.2. ebfm_barwr_imm Procedure
7.6.3. ebfm_barrd_wait Procedure
7.6.4. ebfm_barrd_nowt Procedure
7.6.5. ebfm_cfgwr_imm_wait Procedure
7.6.6. ebfm_cfgwr_imm_nowt Procedure
7.6.7. ebfm_cfgrd_wait Procedure
7.6.8. ebfm_cfgrd_nowt Procedure
7.6.9. BFM Configuration Procedures
7.6.10. BFM Shared Memory Access Procedures
7.6.11. BFM Log and Message Procedures
7.6.12. Verilog HDL Formatting Functions
A.3.1. Intel-Defined VSEC Capability Header (Offset 00h)
A.3.2. Intel-Defined Vendor Specific Header (Offset 04h)
A.3.3. Intel Marker (Offset 08h)
A.3.4. JTAG Silicon ID (Offset 0x0C - 0x18)
A.3.5. User Configurable Device and Board ID (Offset 0x1C - 0x1D)
A.3.6. General Purpose Control and Status Register (Offset 0x30)
A.3.7. Uncorrectable Internal Error Status Register (Offset 0x34)
A.3.8. Uncorrectable Internal Error Mask Register (Offset 0x38)
A.3.9. Correctable Internal Error Status Register (Offset 0x3C)
A.3.10. Correctable Internal Error Mask Register (Offset 0x40)
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8.1.1.3.1. Using the Hard IP Reconfiguration Interface
Refer to the section Hard IP Reconfiguration Interface for details on this interface and the associated address map.
The following table lists the address offsets and bit settings for the PHY status registers. Use the Hard IP Reconfiguration Interface to access these read-only registers.
Offset x16 (Port 0) | Offset x8 (Port 1) | Offset x4 (Ports 2, 3) | Bit Position | Register |
---|---|---|---|---|
0x003EA | 0x003B2 | 0x0035E | [0] | RX polarity |
[1] | RX detection | |||
[2] | RX Valid | |||
[3] | RX Electrical Idle | |||
[4] | TX Electrical Idle | |||
0x003EC | 0x003B4 | 0x00360 | [7] | Framing error |
0x003ED | 0x003B5 | 0x00361 | [7] | Lane reversal |
Follow the steps below to access registers in above table using the Hard IP reconfiguration interface
- Enable the Hard IP reconfiguration interface (User Avalon® -MM interface) using the IP Parameter Editor.
- Set the lane number for which you want to read the status by performing a read-modify-write to the address p#_hip_reconfig_address[20:0] with write data of lane number on p#_hip_reconfig_writedata[7:0] using the Hard IP reconfiguration interface signals.
- p#_hip_reconfig_write = 1’b1
- p#_hip_reconfig_address[20:0] = <offset>
- hip_reconfig_writedata[3:0] = <Lane number>, where Lane number = 4’h0 for lane 0, 4’h1 for lane 1, 4’h2 for lane 2, …
- Read the status of the register you want by performing a read operation from the address hip_reconfig_address[20:0] using the Hard IP reconfiguration interface signals.
- p#_hip_reconfig_read = 1’b1
- p#_hip_reconfig_address[20:0] = <offset>
Offset = Refer to above table for the offset mapping.
- p#_hip_reconfig_readdata[7:0] = Refer to table above for the bit position mapping.
Example: To read the RX detection status of x16 Port 0 Lane0 using the registers
- Enable the Hard IP reconfiguration interface using the IP Parameter Editor.
- Perform read-modify-write to address 0x0003E8 to set the lane number to 0 using the Hard IP reconfiguration interface signals.
- p0_hip_reconfig_write = 1’b1
- p0_hip_reconfig_address[20:0] = 0x003E8
- p0_hip_reconfig_writedata[3:0] = 4'h0
- Read the status of the RX detection register by performing a read operation from the address 0x0003EA[1] using the Hard IP reconfiguration interface signals.
- p0_hip_reconfig_read = 1’b1
- p0_hip_reconfig_address[20:0] = 0x003EA
- p0_hip_reconfig_readdata[1] = 1'b1 (Far end receiver detected)