5.4.1. Avalon-ST RX Interface Signals

F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

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Date 10/11/2023

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5.4.1. Avalon-ST RX Interface Signals

Table 61. Avalon-ST RX Interface Signals
Signal Name	Direction	EP/RP/BP	Clock Domain	Description
`p#_rx_st_data_o[w*128-1:0]`	Output	EP/RP/BP	coreclkout_hip	Avalon-ST Rx data bus. Application receive RX data from Transaction layer via this bus. For Port0 (width=512), TLP with an end-of-packet at the lower 256 bits is allowed to have start-of-packet at the upper 256 bits.
`p#_rx_st_empty_o[p-1:0]`	Output	EP/RP/BP	coreclkout_hip	Specify the number of dwords that are empty during cycles when the `rx_st_eop_o` signals are asserted. These signals are not valid when the `rx_st_eop_o` signals are not asserted.
`p#_rx_st_ready_i`	Input	EP/RP/BP	coreclkout_hip	Indicates the Application Layer is ready to accept data. The readyLatency is 27 cycles. If `rx_st_ready_i` is deasserted by the Application Layer on cycle <n>, the Transaction Layer in the PCIe Hard IP continues to send traffic up to <n>+readyLatency cycles after the deassertion of `rx_st_ready_i`. Once `rx_st_ready_i` reasserts, `rx_st_valid_o` resumes data transfer within readyLatency cycles. To achieve the best performance, the Application Layer must include a receive buffer large enough to avoid the deassertion of `rx_st_ready_i`.
`p#_rx_st_sop_o[n-1:0]`	Output	EP/RP/BP	coreclkout_hip	Signals the first cycle of the TLP when asserted in conjunction with the corresponding bit of `rx_st_valid_o[1:0]`. `rx_st_sop_o[1]`: When asserted, signals the start of a TLP on `rx_st_data_o[511:256]`. `rx_st_sop_o[0]`: When asserted, signals the start of a TLP on `rx_st_data_o[255:0]`.
`p#_rx_st_eop_o[n-1:0]`	Output	EP/RP/BP	coreclkout_hip	Signals the last cycle of the TLP when asserted in conjunction with the corresponding bit of `rx_st_valid_o[1:0]`. `rx_st_eop_o[1]`: When asserted, signals the end of a TLP on `rx_st_data_o[511:256]`. `rx_st_eop_o[0]`: When asserted, signals the end of a TLP on `rx_st_data_o[255:0]`.
`p#_rx_st_valid_o[n-1:0]`	Output	EP/RP/BP	coreclkout_hip	These signals qualify the rx_st_data_o signals going into the Application Layer.
`p#_rx_st_hdr_o[n*128-1:0]`	Output	EP/RP/BP	coreclkout_hip	This is the received header, which follows the TLP header format of the PCIe specifications.
`p#_rx_st_tlp_prfx_o[n*32-1:0]`	Output	EP/RP/BP	coreclkout_hip	This is the first TLP prefix received, which follows the TLP prefix format of the PCIe specifications. PASID is included. These signals are valid when the corresponding rx_st_sop_o is asserted. The TLP prefix uses a Big Endian implementation (i.e, the Fmt field is in bits [31:29] and the Type field is in bits [28:24]). If no prefix is present for a given TLP, that dword (including the Fmt field) is all zeros.
`p#_rx_st_vf_active_o[n-1:0]`	Output	EP	coreclkout_hip	Note: Not available for p2 and p3. When asserted, these signals indicate that the received TLP is targeting a virtual function. When these signals are deasserted, the received TLP is targeting a physical function and the rx_st_func_num signals indicate the function number. These signals are valid when the corresponding rx_st_sop_o is asserted. These signals are multiplexed with the rx_st_hdr_o signals in the x4 configuration. These signals are valid in Endpoint mode only.
`p#_rx_st_func_num_o[p-1:0]`	Output	EP	coreclkout_hip	Note: Not available for p2 and p3. Specify the target physical function number for the received TLP. These signals are valid when the corresponding rx_st_sop_o is asserted. These signals are multiplexed with the rx_st_hdr_o signals in the x4 configuration. These signals are valid in Endpoint mode only.
`p#_rx_st_vf_num_o[n*11-1:0]`	Output	EP	coreclkout_hip	Note: Not available for p2 and p3. Specify the target VF mnumber for the received TLP. The application uses this information for both request and completion TLPs. For a completion TLP, these bits specify the VF number of the requester for this completion TLP. These signals are valid when rx_st_vf_active_o and the corresponding rx_st_sop_o are asserted. These signals are multiplexed with the rx_st_hdr_o signals in the x4 configuration. These signals are valid in Endpoint mode only.
`p#_rx_st_bar_range_o[p-1:0]`	Output	EP/RP/BP	coreclkout_hip	Specify the BAR for the TLP being output. For each BAR range, the following encodings are defined: 000: Memory BAR 0 001: Memory BAR 1 010: Memory BAR 2 011: Memory BAR 3 100: Memory BAR 4 101: Memory BAR 5 110: I/O BAR 111: Expansion ROM BAR These outputs are valid when both `rx_st_sop_o` and `rx_st_valid_o` are asserted.
`p#_rx_st_tlp_abort_o[n-1:0]`	Output	BP	coreclkout_hip	Indicates to application to drop the TLP because of ECRC error. You should not expect the TLP to be replayed. By default, PCIe hip drop errored TLP. Operating in TLP Bypass mode, errored TLPs will be forwarded to the RX packet interface. This output is valid when rx_st_valid_o is asserted.
`p#_rx_st_data_par_o[w*16-1:0]`	Output	EP/RP/BP	coreclkout_hip	Byte parity signals for `rx_st_data_o`. These parity signals are not available when ECC is enabled.
`p#_rx_st_hdr_par_o[n*16-1:0]`	Output	EP/RP/BP	coreclkout_hip	Byte parity signals for `rx_st_hdr_o`. These parity signals are not available when ECC is enabled.
`p#_rx_st_tlp_prfx_par_o[n*4-1:0]`	Output	EP/RP/BP	coreclkout_hip	Byte parity signals for rx_st_tlp_prfx_o. These parity signals are not available when ECC is enabled.
`p#_rx_par_err_o`	Output	EP/RP/BP	coreclkout_hip	Asserted for a single cycle to indicate that a parity error was detected in a TLP at the input of the RX buffer. This error is logged as an uncorrectable internal error in the VSEC registers. If this error occurs, you must reset the Hard IP because parity errors can leave the Hard IP in an unknown state.

Table 62. RX Flow Control Interface Signals
Signal Name	Direction	EP/RP/BP	Clock Domain	Description
`p#_rx_buffer_limit_tdm_indx_i[1:0]`	Input	EP/RP/BP	coreclkout_hip	These signals indicate the type of buffer for the corresponding `rx_buffer_limit_i[11:0]` signals. The Application Layer should provide the buffer limit information for all the enabled ports in a TDM manner. The following encodings are defined: 00: buffer limit for P type of TLPs. 01: buffer limit for NP type. 10: buffer limit for CPL type. 11: reserved.
`p#_rx_buffer_limit_i[11:0]`	Input	EP/RP/BP	coreclkout_hip	When the RX Flow Control Interface is enabled, the application can use these signals for TLP flow control. These signals indicate the application RX buffer space made available since reset/initialization. Initially, the signals are set according to the buffer size (in terms of the number of TLPs the RX buffer can take). The value of these signals always increments and rolls over. For example, if the initial value is 0xfff, the `rx_buffer_limit_i[11:0]` value increments by 1 and rolls over to 0x000 when one received TLP exits the application RX buffer. If a TLP type is blocked due to a lack of the corresponding RX buffer space in the application layer, other TLP types may bypass it per the PCIe transaction ordering rules. Note that the initial value of `rx_buffer_limit_i[11:0]` cannot be larger than 2048 TLPs.