Visible to Intel only — GUID: gji1613962840831
Ixiasoft
Visible to Intel only — GUID: gji1613962840831
Ixiasoft
3.1.1. Clocks
- PHY clock domain (core_clk domain): This clock is synchronous to the SerDes parallel clock.
- EMIB/FPGA fabric interface clock domain (pld_clk domain): This clock is generated from a System PLL. The System PLL could share the same reference clock used by the SerDes or a separate reference clock.
- Application clock domain (coreclkout_hip): this clock is an output from the F-Tile IP, and it has the same frequency as pld_clk.
The PHY clock domain (core_clk domain) is a dynamic frequency domain. The PHY clock frequency is dependent on the current link speed.
Link Speed | PHY Clock Frequency | Application Clock Frequency |
---|---|---|
Gen1 | 125 MHz | Gen1 is supported only via link downtraining and not natively. Hence, the application clock frequency depends on the configuration you select in the IP Parameter Editor. For example, if you select a Gen3 configuration, the application clock frequency is 250 MHz. |
Gen2 | 250 MHz | Gen2 is supported only via link downtraining and not natively. Hence, the application clock frequency depends on the configuration you select in the IP Parameter Editor. For example, if you select a Gen3 configuration, the application clock frequency is 250 MHz. |
Gen3 | 500 MHz | 250 MHz |
Gen4 | 1000 MHz | 500 MHz / 450 MHz / 400 MHz / 350 MHz / 250 MHz / 225 MHz / 200 MHz / 175 MHz
Note: As the data width remains unchanged, using lower frequency results in lower data throughput.
|