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2.6. IP Core and Design Example Support Levels
The following table shows the support levels of the Avalon® -ST IP core and design example in Intel® Agilex™ 7 devices.
Configuration | PCIe IP Support | Design Example Support | ||||
---|---|---|---|---|---|---|
End Point | Root Port | TLP-Bypass | End Point | Root Port | TLP Bypass | |
Gen4 x16 512-bit |
S, C, T, H | S, C, T, H | S, C, T, H | S,C,T, H | N/A | N/A |
Gen4 x16 (250 MHz / 225 MHz / 200 MHz / 175 MHz) 512-bit |
S, C, T, H |
S, C, T, H |
S, C, T, H |
N/A | N/A | N/A |
Gen4 x8/x8 256-bit |
S, C, T, H | N/A | S, C, T, H | S,C,T, H | N/A | N/A |
Gen4 x8/x8 512-bit |
S, C, T, H |
N/A |
S, C, T, H |
N/A | N/A | N/A |
Gen4 x8/x8 (250 MHz / 225 MHz / 200 MHz / 175 MHz) 256-bit |
S, C, T, H |
N/A |
S, C, T, H |
N/A | N/A | N/A |
Gen4 x8 256-bit |
S, C, T, H | S, C, T, H | N/A | S,C,T, H | N/A | N/A |
Gen4 x4/x4/x4/x4 128-bit |
N/A | S, C, T, H | S, C, T, H | N/A | N/A | N/A |
Gen4 x4/x4 128-bit |
N/A | S, C, T, H | N/A | N/A | N/A | N/A |
Gen4 x4 128-bit |
S, C, T, H | N/A | N/A | N/A | N/A | N/A |
Gen3 x16 512-bit |
S, C, T, H | S, C, T, H | S, C, T, H | S,C,T, H | N/A | N/A |
Gen3 x16 256-bit |
S, C, T, H |
S, C, T, H |
S, C, T, H |
N/A | N/A | N/A |
Gen3 x8/x8 256-bit |
S, C, T, H | N/A | S, C, T, H | S,C,T, H | N/A | N/A |
Gen3 x8 256-bit |
S, C, T, H | S, C, T, H | N/A | S,C,T, H | N/A | N/A |
Gen3 x4/x4/x4/x4 128-bit |
N/A | S, C, T, H | S, C, T, H | N/A | N/A | N/A |
Gen3 x4/x4 128-bit |
N/A | S, C, T, H | N/A | N/A | N/A | N/A |
Gen3 x4 128-bit |
S, C, T, H | N/A | N/A | N/A | N/A | N/A |