GPIO Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

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ID 683136
Date 9/13/2023
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Document Table of Contents
Document Table of Contents x
GPIO Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
GPIO Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices x
Release Information for GPIO Intel® FPGA IP GPIO Intel® FPGA IP Features GPIO Intel® FPGA IP Data Paths GPIO Intel® FPGA IP Interface Signals Verifying Resource Utilization and Design Performance GPIO Intel® FPGA IP Parameter Settings Register Packing GPIO Intel® FPGA IP Timing GPIO Intel® FPGA IP Design Examples IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices Intel® Arria® 10 and Intel® Cyclone® 10 GX GPIO Intel® FPGA IP User Guide Archives Document Revision History for GPIO Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
GPIO Intel® FPGA IP Data Paths x
Input Path Output and Output Enable Paths
GPIO Intel® FPGA IP Interface Signals x
Shared Signals Data Bit-Order for Data Interface Input and Output Bus High and Low Bits Input Bus Output Bus Data Interface Signals and Corresponding Clocks
GPIO Intel® FPGA IP Timing x
Timing Components Delay Elements Timing Analysis Timing Closure Guidelines
Timing Analysis x
Single Data Rate Input Register Full-Rate or Half-Rate DDIO Input Register Single Data Rate Output Register Full-Rate or Half-Rate DDIO Output Register
GPIO Intel® FPGA IP Design Examples x
GPIO Intel® FPGA IP Synthesizable Intel® Quartus® Prime Design Example GPIO Intel® FPGA IP Simulation Design Example
IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices x
Migrating Your ALTDDIO_IN, ALTDDIO_OUT, ALTDDIO_BIDIR, and ALTIOBUF IP Cores Guideline: Swap datain_h and datain_l Ports in Migrated IP
GPIO Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

Input and Output Bus High and Low Bits

The high and low bits in the input or output signals are included in the din and dout input and output buses.

Input Bus

For the din bus, if datain_h and datain_l are the high and low bits, with each width being datain_width:

  • datain_h = din[(2 × datain_width - 1):datain_width]
  • datain_l = din[(datain_width - 1):0]

For example, for din[7:0] = 8'b11001010:

  • datain_h = 4'b1100
  • datain_l = 4'b1010

Output Bus

For the dout bus, if dataout_h and dataout_l are the high and low bits, with each width being dataout_width:

  • dataout_h = dout[(2 × dataout_width - 1):dataout_width]
  • dataout_l = dout[(dataout_width - 1):0]

For example, for dout[7:0] = 8'b11001010:

  • dataout_h = 4'b1100
  • dataout_l = 4'b1010
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