Visible to Intel only — GUID: sam1412835885407
Ixiasoft
Release Information for GPIO Intel® FPGA IP
GPIO Intel® FPGA IP Features
GPIO Intel® FPGA IP Data Paths
GPIO Intel® FPGA IP Interface Signals
Verifying Resource Utilization and Design Performance
GPIO Intel® FPGA IP Parameter Settings
Register Packing
GPIO Intel® FPGA IP Timing
GPIO Intel® FPGA IP Design Examples
IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices
GPIO Intel® FPGA IP User Guide Archives
Document Revision History for GPIO Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
Visible to Intel only — GUID: sam1412835885407
Ixiasoft
GPIO Intel® FPGA IP Timing
The performance of the GPIO IP core depends on the I/O constraints and clock phases. To validate the timing for your GPIO configuration, Intel recommends that you use the Timing Analyzer.