GPIO Intel® FPGA IP Parameter Settings
Parameter | Condition | Allowed Values | Description |
---|---|---|---|
Data Direction | — |
|
Specifies the data direction for the GPIO. |
Data width | — | 1 to 128 |
Specifies the data width. |
Use legacy top-level port names | — |
|
Use same port names as in Stratix® V, Arria® V, and Cyclone® V devices. For example, dout becomes dataout_h and dataout_l, and din becomes datain_h and datain_l.
Note: The behavior of these ports are different than in the Stratix® V, Arria® V, and Cyclone® V devices. For the migration guideline, refer to the related information.
|
Parameter | Condition | Allowed Values | Description |
---|---|---|---|
Use differential buffer | — |
|
If turned on, enables differential I/O buffers. |
Use pseudo differential buffer |
|
|
If turned on in output mode, enables pseudo differential output buffers. This option is automatically turned on for bidirectional mode if you turn on Use differential buffer. |
Use bus-hold circuitry |
|
|
If turned on, the bus hold circuitry can weakly hold the signal on an I/O pin at its last-driven state where the output buffer state will be 1 or 0 but not high-impedance. |
Use open drain output |
|
|
If turned on, the open drain output enables the device to provide system-level control signals such as interrupt and write enable signals that can be asserted by multiple devices in your system. |
Enable output enable port | Data Direction = Output |
|
If turned on, enables user input to the OE port. This option is automatically turned on for bidirectional mode. |
Enable seriestermination / paralleltermination ports | — |
|
If turned on, enables the seriesterminationcontrol and parallelterminationcontrol ports of the output buffer. |
Parameter | Condition | Allowed Values | Description |
---|---|---|---|
Register mode | — |
|
Specifies the register mode for the GPIO IP core:
|
Enable synchronous clear / preset port |
|
|
Specifies how to implement synchronous reset port.
|
Enable asynchronous clear / preset port |
|
|
Specifies how to implement asynchronous reset port.
ACLR and ASET signals are active high. |
Enable clock enable ports | Register mode = DDIO |
|
|
Half Rate logic | Register mode = DDIO |
|
If turned on, enables half-rate DDIO. |
Separate input / output Clocks |
|
|
If turned on, enables separate clocks (CK_IN and CK_OUT) for the input and output paths in bidirectional mode. |