November 2017 |
2017.11.06 |
- Added support for Intel® Cyclone® 10 GX devices.
- Updated the signal names in figures to match the signal names in the GPIO IP core.
- Added the output path waveform.
- Renamed "Altera GPIO IP core" to "Intel FPGA GPIO IP core".
- Renamed "Altera IOPLL IP core" to "Intel FPGA IOPLL IP core".
- Renamed "TimeQuest Timing Analyzer" to "Timing Analyzer".
- Renamed "Qsys" to "Platform Designer".
- Clarified that the ASET and ACLR signals are active high.
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May 2017 |
2017.05.08 |
- Updated the table listing the GPIO buffer parameters to specify the conditions for the Use bus-hold circuitry parameter option.
- Rebranded as Intel.
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October 2016 |
2016.10.31 |
- Updated the input path waveform.
- Added a topic describing the high and low bits in the din and dout buses.
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August 2016 |
2016.08.05 |
- Added notes about dynamic OCT support in the GPIO IP core.
- Updated the topic about parameter settings to improve accuracy and clarity.
- Updated the section about generating the design example.
- Added a guideline topic about behavior of the legacy ports when you migrate to the GPIO IP core from Stratix® V, Arria® V, and Cyclone® V devices.
- Rewrote and restructured the document to improve clarity and for ease of reference.
- Changed instances of Quartus II to Quartus Prime.
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August 2014 |
2014.08.18 |
- Added timing information.
- Added register packing information.
- Added Use legacy top-level port names parameter. This is a new parameter.
- Added register packing information.
- Replaced the term megafunction with IP core.
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November 2013 |
2013.11.29 |
Initial release. |